LTC3835 Linear Technology, LTC3835 Datasheet - Page 8
![no-image](/images/manufacturer_photos/0/3/388/linear_technology_sml.jpg)
LTC3835
Manufacturer Part Number
LTC3835
Description
Low IQ Synchronous Step-Down Controller
Manufacturer
Linear Technology
Datasheet
1.LTC3835.pdf
(28 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LTC3835EDHC-1
Manufacturer:
LT
Quantity:
10 000
Part Number:
LTC3835EDHC-1
Manufacturer:
LTNRAR
Quantity:
20 000
Part Number:
LTC3835EDHC-1#PBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
Part Number:
LTC3835EDHC-1#TRPBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
Company:
Part Number:
LTC3835EGN-1
Manufacturer:
LT
Quantity:
10 000
Part Number:
LTC3835EGN-1
Manufacturer:
LINEAR/凌特
Quantity:
20 000
Part Number:
LTC3835EGN-1#PBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
Company:
Part Number:
LTC3835EUFD
Manufacturer:
LT
Quantity:
10 000
Company:
Part Number:
LTC3835IDHC-1
Manufacturer:
LT
Quantity:
10 000
Company:
Part Number:
LTC3835IGN-1
Manufacturer:
LT
Quantity:
10 000
www.datasheet4u.com
LTC3835
PIN FUNCTIONS
8
CLKOUT (Pin 1/Pin 19): Open-Drain Output Clock Signal
available to daisychain other controller ICs for additional
MOSFET driver stages/phases.
PLLLPF (Pin 2/Pin 20): The phase-locked loop’s lowpass
fi lter is tied to this pin when synchronizing to an external
clock. Alternatively, tie this pin to GND, V
to select 250kHz, 530kHz or 400kHz switching frequency.
I
Regulator Compensation Points. The current comparator
trip point increases with this control voltage.
TRACK/SS (Pin 4/Pin 2): External Tracking and Soft-Start
Input. The LTC3835 regulates the V
of 0.8V or the voltage on the TRACK/SS pin. A internal 1μA
pull-up current source is connected to this pin. A capacitor
to ground at this pin sets the ramp time to fi nal regulated
output voltage. Alternatively, a resistor divider on another
voltage supply connected to this pin allows the LTC3835
output to track the other supply during startup.
V
age from an external resistive divider across the output.
SGND (Pin 6/Pin 4): Small Signal Ground. Must be routed
separately from high current grounds to the common (–)
terminals of the input capacitor.
PGND (Pin 7/Pin 5): Driver Power Ground. Connects to the
source of bottom (synchronous) N-channel MOSFET, anode
of the Schottky rectifi er and the (–) terminal of C
BG (Pin 8/Pin 6): High Current Gate Drive for Bottom
(Synchronous) N-Channel MOSFET. Voltage swing at this
pin is from ground to INTV
INTV
Dropout Regulator. The driver and control circuit are
powered from this voltage source. Must be decoupled to
power ground with a minimum of 4.7μF tantalum or other
low ESR capacitor.
EXTV
Connected to INTV
ing the internal LDO powered from V
higher than 4.7V . See EXTV
Information section. Do not exceed 10V on this pin.
TH
FB
(Pin 3/Pin 1): Error Amplifi er Outputs and Switching
(Pin 5/Pin 3): Receives the remotely sensed feedback volt-
CC
CC
(Pin 10/Pin 8): External Power Input to an Internal LDO
(Pin 9/Pin 7): Output of the Internal Linear Low
CC
. This LDO supplies V
CC
CC
(FE Package/UFD Package)
Connection in the Applications
.
FB
IN
voltage to the smaller
whenever EXTV
IN
CC
or leave fl oating
power, bypass-
IN
.
CC
is
V
be tied between this pin and the signal ground pin.
SW (Pin 12/Pin 10): Switch Node Connections to Inductor.
Voltage swing at this pin is from a Schottky diode (external)
voltage drop below ground to V
TG (Pin 13/Pin 11): High Current Gate Drive for Top
N-Channel MOSFET. These are the outputs of fl oating drivers
with a voltage swing equal to INTV
on the switch node voltage SW.
BOOST (Pin 14/Pin 12): Bootstrapped Supply to the Top
Side Floating Driver. A capacitor is connected between the
BOOST and SW pins and a Schottky diode is tied between
the BOOST and INTV
pin is from INTV
RUN (Pin 15/Pin 13): Digital Run Control Input for
Controller. Forcing this pin below 0.7V shuts down all
controller functions, reducing the quiescent current that
the LTC3835 draws to approximately 10μA.
SENSE– (Pin 16/Pin 14): The (–) Input to the Differential
Current Comparator.
SENSE+ (Pin 17/Pin 15): The (+) Input to the Differential
Current Comparator. The I
offsets between the SENSE– and SENSE+ pins in conjunc-
tion with R
PGOOD (Pin 18/Pin 16): Open-Drain Logic Output. PGOOD
is pulled to ground when the voltage on the V
within ±10% of its set point.
PLLIN/MODE (Pin 19/Pin 17): External Synchronization
Input to Phase Detector and Forced Continuous Control
Input. When an external clock is applied to this pin, the
phase-locked loop will force the rising TG signal to be
synchronized with the rising edge of the external clock. In
this case, an R-C fi lter must be connected to the PLLLPF
pin. When not synchronizing to an external clock, this
input determines how the LTC3835 operates at light loads.
Pulling this pin below 0.7V selects Burst Mode operation.
Tying this pin to INTV
operation. Tying this pin to a voltage greater than 0.9V and
less than INTV
IN
(Pin 11/Pin 9): Main Supply Pin. A bypass capacitor should
SENSE
CC
CC
set the current trip threshold.
selects pulse-skipping operation.
to (V
CC
CC
forces continuous inductor current
pins. Voltage swing at the BOOST
IN
+ INTV
TH
pin voltage and controlled
IN
CC
.
CC
– 0.5V superimposed
).
FB
pin is not
3835fc