FS612509-02 ETC, FS612509-02 Datasheet

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FS612509-02

Manufacturer Part Number
FS612509-02
Description
1:9 ZERO DELAY CLOCK BUFFER IC
Manufacturer
ETC
Datasheet
November 2000
1.0
Figure 1: Block Diagram
This document contains information on a new product. Specifications and information herein are subject to change without notice.
ISO9001
ISO9001
AMERICAN MICROSYSTEMS, INC.
ISO9001
ISO9001
QS9000
QS9000
QS9000
QS9000
FBIN
AGND
AVDD
CLK
Generates one bank of five outputs (1Y0 to 1Y4) and
one bank of four outputs (2Y0 to 2Y3) from one ref-
erence clock input (CLK)
Designed to meet the PLL Component Specifications
as noted in the PC133 SDRAM Registered DIMM
Design Specification
External feedback input (FBIN) to synchronize all
clock outputs to the clock input
Operating frequency: 25MHz to 140MHz
Tight tracking skew (spread-spectrum tolerant)
On-chip 25 series damping resistors for driving
point-to-point loads
Separate bank controls:
M
M
Available with an auto power-down option that turns
off the PLL and forces all outputs low when the refer-
ence clock stops (FS612509-02)
Packaged in a 24-pin TSSOP
1G
2G
Features
Signal 1G enables or disables outputs 1Y0 - 1Y4
Signal 2G enables or disables outputs 2Y0 - 2Y3
FS612509
PLL
VDD
1Y0
1Y1
1Y2
1Y3
1Y4
2Y0
2Y1
2Y2
2Y3
FBOUT
GND
2.0
The FS612509 is a low skew, low jitter CMOS zero-delay
phase-lock loop (PLL) clock buffer IC designed for high-
speed motherboard applications, such as those using
133MHz SDRAM.
Nine buffered clock outputs are derived from an onboard
open-loop PLL. The PLL aligns the frequency and phase
of all output clocks to the input clock CLK, including an
FBOUT clock that feeds back to FBIN to close the loop.
One group of five outputs 1Y0 to 1Y4 are enabled and
disabled low by the active-high 1G signal. A second
group of four outputs 2Y0 to 2Y3 are enabled and dis-
abled low by the active-high 2G signal. The PLL may be
bypassed by pulling AVDD to ground.
Figure 2: Pin Configuration
Table 1: Function Table
PLL
AVDD
H
H
H
H
H
L
L
L
L
L
Description
1:9 Zero-Delay Clock Buffer IC
1:9 Zero-Delay Clock Buffer IC
1:9 Zero-Delay Clock Buffer IC
1:9 Zero-Delay Clock Buffer IC
FBOUT
1G
H
H
H
H
H
H
AGND
L
L
L
L
INPUT
GND
GND
VDD
VDD
FS612509-01/-02
FS612509-01/-02
FS612509-01/-02
FS612509-01/-02
1Y0
1Y1
1Y2
1Y3
1Y4
1G
2G
10
11
12
H
H
H
H
H
H
L
L
L
L
1
2
3
4
5
6
7
8
9
CLK
H
H
H
H
H
H
H
H
L
L
1Y0-1Y4
H
H
H
H
L
L
L
L
L
L
24
23
22
21
20
19
18
17
16
15
14
13
CLK
AVDD
VDD
2Y0
2Y1
GND
GND
2Y2
2Y3
VDD
2G
FBIN
OUTPUT
2Y0-2Y3
H
H
H
H
L
L
L
L
L
L
FBOUT
11.29.00
H
H
H
H
H
H
H
H
L
L

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FS612509-02 Summary of contents

Page 1

... Signal 1G enables or disables outputs 1Y0 - 1Y4 M Signal 2G enables or disables outputs 2Y0 - 2Y3 Available with an auto power-down option that turns off the PLL and forces all outputs low when the refer- ence clock stops (FS612509-02) Packaged in a 24-pin TSSOP Figure 1: Block Diagram 1G AVDD ...

Page 2

... FS612509-01/-02 FS612509-01/-02 FS612509-01/-02 FS612509-01/-02 1:9 Zero-Delay Clock Buffer IC 1:9 Zero-Delay Clock Buffer IC 1:9 Zero-Delay Clock Buffer IC 1:9 Zero-Delay Clock Buffer IC Table 2: Pin Descriptions Key Analog Input Analog Output Digital Input Digital Output Power/Ground Active Low pin PIN TYPE NAME 1Y0 ...

Page 3

... Power-Down The FS612509-02 version provides an auto power-down feature that shuts off the PLL, drives all outputs low, and places the device into a low current state if the reference clock stops. The power-down circuit is level sensitive, and detects either a DC high or low on the CLK input ...

Page 4

... FS612509-01/-02 FS612509-01/-02 FS612509-01/-02 FS612509-01/-02 1:9 Zero-Delay Clock Buffer IC 1:9 Zero-Delay Clock Buffer IC 1:9 Zero-Delay Clock Buffer IC 1:9 Zero-Delay Clock Buffer IC 5.0 Electrical Specifications Table 3: Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied ...

Page 5

... FS612509-01/-02 FS612509-01/-02 FS612509-01/-02 FS612509-01/-02 1:9 Zero-Delay Clock Buffer IC 1:9 Zero-Delay Clock Buffer IC 1:9 Zero-Delay Clock Buffer IC 1:9 Zero-Delay Clock Buffer IC MIN. TYP. MAX. 130 3 2 -0 -0.3 0 -18 -12 -35 ...

Page 6

... FS612509-01/-02 FS612509-01/-02 FS612509-01/-02 FS612509-01/-02 1:9 Zero-Delay Clock Buffer IC 1:9 Zero-Delay Clock Buffer IC 1:9 Zero-Delay Clock Buffer IC 1:9 Zero-Delay Clock Buffer IC Table 7: AC Timing Specifications Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature T are not currently production tested to any specific limits. MIN and MAX characterization data are ...

Page 7

... L Longest lead to any Longest lead Longest lead to any Longest lead to any FS612509-01/-02 FS612509-01/-02 FS612509-01/-02 FS612509-01/-02 1:9 Zero-Delay Clock Buffer IC 1:9 Zero-Delay Clock Buffer IC 1:9 Zero-Delay Clock Buffer IC 1:9 Zero-Delay Clock Buffer SEATING PLANE ...

Page 8

... FS612509-01 12055-802 12055-803 FS612509-02 Copyright © 2000 American Microsystems, Inc. Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI re- serves the right to discontinue production and change specifications and prices at any time and without notice. AMI’ ...

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