MBM29DL324TD Fujitsu Media Devices, MBM29DL324TD Datasheet - Page 70

• Manufacturer Part Number: MBM29DL324TD
• Description: (MBM29DL32xBD) 32M (4M X 8/2M X 16) BIT Dual Operation
• Manufacturer: Fujitsu Media Devices

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MBM29DL32XTD/BD
Note: Successive reads from the erasing or erase-suspend sector will cause DQ
Ready/Busy
Program
Erase
Erase-Suspend Read
(Erase-Suspended Sector)
Erase-Suspend Program
For example, DQ
(DQ
Furthermore, DQ
mode, DQ
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
• RY/BY
The MBM29DL32XTD/BD provide a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are
busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/
write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase
commands. If the MBM29DL32XTD/BD are placed in an Erase Suspend mode, the RY/BY output will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate
a busy condition during the RESET pulse. Refer to Figures 13 and 14 for a detailed timing diagram. The RY/BY
pin is pulled high in standby mode.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to V
• Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29DL32XTD/BD devices. When
this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ
to DQ
becomes the lowest address bit and DQ
an 8-bit operation and hence commands are written at DQ
to Figures 15, 16 and 17 for the timing diagram.
• Data Protection
The MBM29DL32XTD/BD are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices
automatically reset the internal state machine in the Read mode. Also, with its control register architecture,
alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command
sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form V
and power-down transitions or system noise.
erase suspend sector address will indicate logic “1” at the DQ
2
toggles while DQ
15
. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ
2
toggles if this bit is read from an erasing sector.
Mode
2
2
and DQ
can also be used to determine which sector is being erased. When the device is in the erase
6
does not.) See also Table 14 and Figure 12.
6
can be used together to determine if the erase-suspend-read mode is in progress.
Table 14 Toggle Bit Status
8
-80/90/12
to DQ
DQ
DQ
DQ
0
1
14
7
7
7
bits are tri-stated. However, the command bus cycle is always
0
to DQ
2
7
and the DQ
bit.
Toggle
Toggle
Toggle
DQ
1
6
2
8
to toggle. Reading from non-
to DQ
15
bits are ignored. Refer
Toggle (Note)
1 (Note)
Toggle
DQ
1
CC
2
power-up
15
/A
CC
-1
.
pin
0