MBM29DL400BC Fujitsu Media Devices, MBM29DL400BC Datasheet - Page 24

• Manufacturer Part Number: MBM29DL400BC
• Description: 4M (512K X 8/256K X 16) BIT
• Manufacturer: Fujitsu Media Devices

24
MBM29DL400TC
DQ
Exceeded Timing Limits
DQ
Sector Erase Timer
DQ
Toggle Bit II
The system can use DQ
is actively erasing (that is, the Embedded Erase Algorithm is in progress), DQ
Erase Suspend mode, DQ
DQ
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
See Figure 10 for the Toggle Bit I timing specifications and diagrams.
DQ
these conditions DQ
cycle was not successfully completed. Data Polling is the only operating function of the devices under this
condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA).
The OE and WE pins will control the output disable functions as described in Tables 2 and 3.
The DQ
case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ
DQ
used. If this occurs, reset the device with command sequence.
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ
be used to determine if the sector erase timer window is still open. If DQ
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ
additional sector erase commands. To insure the command has been accepted, the system software should
check the status of DQ
the second status check, the command may not have been accepted.
See Table 9: Hardware Sequence Flags.
This toggle bit II, along with DQ
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ
devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ
address of the non-erase suspended sector will indicate a logic “1” at the DQ
DQ
Program operation is in progress. The behavior of these two status bits, along with that of DQ
as follows:
5
3
2
6
5
5
2
6
bit will indicate a “1.” Please note that this is not a device failure condition since the devices were incorrectly
to toggle.
will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte
is different from DQ
5
failure condition may also appear if a user tries to program a non blank location without erasing. In this
5
will produce a “1”. This is a failure condition which indicates that the program or erase
3
6
prior to and following each subsequent Sector Erase command. If DQ
7
to determine whether a sector is actively erasing or is erase-suspended. When a bank
2
bit and DQ
6
in that DQ
stops toggling. Successive read cycles during the erase-suspend-program cause
-55/-70/-90/-12
6
, can be used to determine whether the devices are in the Embedded Erase
6
6
never stops toggling. Once the devices have exceeded timing limits, the
toggles only when the standard program or Erase, or Erase Suspend
/MBM29DL400BC
2
to toggle during the Embedded Erase Algorithm. If the
3
is high (“1”) the internally controlled
3
is low (“0”), the device will accept
6
2
toggles. When a bank enters the
bit.
-55/-70/-90/-12
7
, is summarized
3
were high on
3
3
may
will