psmn005-25d-hg NXP Semiconductors, psmn005-25d-hg Datasheet - Page 8

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psmn005-25d-hg

Manufacturer Part Number
psmn005-25d-hg
Description
Psmn005-25d N-channel Logic Level Trenchmos Tm Transistor
Manufacturer
NXP Semiconductors
Datasheet
Philips Semiconductors
October 1999
MECHANICAL DATA
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
N-channel logic level TrenchMOS
discharge during transport or handling.
Fig.16. SOT428 surface mounting package. Centre pin connected to mounting base.
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped)
Note
1. Measured from heatsink back to lead.
DIMENSIONS (mm are the original dimensions)
UNIT
mm
OUTLINE
VERSION
SOT428
max.
2.38
2.22
L 2
A
A 1
0.65
0.45
(1)
b 1
0.89
0.71
A 2
1
e
0.89
0.71
b 2
e 1
IEC
E
b
2
max.
1.1
0.9
b 1
b
5.36
5.26
b 2
3
JEDEC
w
0.4
0.2
D
L
A
c
M
H E
REFERENCES
A
max.
6.22
5.98
D
(TM)
mounting
0
max.
4.81
4.45
base
D 1
seating plane
L 1
A 1
max.
scale
6.73
6.47
EIAJ
8
transistor
10
E
c
A 2
min.
4.0
A
E 1
20 mm
y
2.285 4.57
e
e 1
E 1
max.
10.4
H E
9.6
2.95
2.55
L
PROJECTION
EUROPEAN
min.
0.5
L 1
D 1
0.7
0.5
L 2
0.2
w
ISSUE DATE
98-04-07
max.
0.2
y
PSMN005-25D
SOT428
Product specification
Rev 1.100

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