cy2sstu32866 SpectraLinear Inc, cy2sstu32866 Datasheet - Page 2

• Manufacturer Part Number: cy2sstu32866
• Description: 1.8v, 25-bit 1 1 Or 14-bit 1 2 Jedec-compliant Data Register With Parity
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 25, 2006
The CY2SSTV32866 accepts a parity bit from the memory
controller on its parity bit (PAR_IN) input, compares it with the
data received on the DIMM-independent D-inputs and
indicates whether a parity error has occurred on its open-drain
QERR# pin (active LOW). The convention is even parity, i.e.,
valid parity is defined as an even number of ones across the
DIMM-independent data inputs combined with the parity input
bit.
When used as a single device, the C0 and C1 inputs are tied
LOW. In this configuration, parity is checked on the PAR_IN
input which arrives one cycle after the input data to which it
applies. The partial-parity-out (PPO) and QERR# signals are
produced three cycles after the corresponding data inputs.
When used in pairs, the C0 input of the first register is tied
LOW and the C0 input of the second register is tied HIGH. The
Table 1. Parity Function Table
Pin Definition
GND
VDD
VREF
ZOH
ZOL
CK
CK#
C0
C1
Pin Name
RESET#
H
H
H
H
H
H
H
H
H
H
L
B3, B4, D3, D4, F3, F4,
H3, H4, K3, K4, M3, M4,
P3, P4
A4, C3, C4, E3, E4, G3,
G4, J3, J4, L3, L4, N3,
N4, R3, R4, T4
A3, T3
J5
J6
H1
J1
G6
G5
Floating
(C0 = 0, C1 = 0)
DCS#
X or
Pin Number
H
H
H
H
H
X
L
L
L
L
Floating
CSR#
X or
H
X
X
X
X
L
L
L
L
X
B3, B4, D3, D4, F3,
F4, H3, H4, K3, K4,
M3, M4, P3, P4
A4, C3, C4, E3,
E4, G3, G4, J3, J4,
L3, L4, N3, N4, R3,
R4, T4
A3, T3
J5
J6
H1
J1
G6
G5
(C0 = 0, C1 = 1)
Pin Number
Floating
L or H
X or
CK
Inputs
↓↑
↓↑
↓↑
↓↑
↓↑
↓↑
↓↑
↓↑
↓↑
Floating
L or H
CK#
X or
↓↑
↓↑
↓↑
↓↑
↓↑
↓↑
↓↑
↓↑
↓↑
B3, B4, D3, D4, F3,
F4, H3, H4, K3, K4,
M3, M4, P3, P4
A4, C3, C4, E3,
E4, G3, G4, J3, J4,
L3, L4, N3, N4, R3,
R4, T4
A3, T3
J5
J6
H1
J1
G6
G5
(C0 = 1, C1 = 1)
Pin Number
C1 input of both registers are tied HIGH. Parity, which arrives
one cycle after the data input to which it applies, is checked on
the PAR_IN input of the first device. The PPO and QERR#
signals are produced on the second device three clock cycles
after the corresponding data inputs. The PPO output of the first
register is cascaded to the PAR_IN of the second register. The
QERR# output of the first register is left floating and the valid
error information is latched on the QERR# output of the
second register. If an error occurs and the QERR# output is
driven LOW, it stays latched LOW for two clock cycles or until
RESET# is driven LOW. The DIMM-dependent signals
(DCKE, DCS#, DODT, and CSR#) are not included in the
parity check computation.
Parity is calculated using Table 1.
Sum of inputs =
X or Floating
H (D1-25)
Even
Even
Even
Even
Odd
Odd
Odd
Odd
X
X
Ground
Power Supply Voltage
Input Reference Voltage
Reserved
Reserved
Positive Master Clock
Negative Master Clock
Configuration control input
Configuration control input
PAR_IN
Floating
X or
H
H
H
H
X
X
L
L
L
L
CY2SSTU32866
Description
PPO
PPO
PPO
H
H
H
H
L
L
L
L
L
0
0
Outputs
Page 2 of 24
QERR#
QERR#
QERR#
H
H
H
H
H
L
L
L
L
0
0