ds2431pt-r Maxim Integrated Products, Inc., ds2431pt-r Datasheet
ds2431pt-r
Related parts for ds2431pt-r
ds2431pt-r Summary of contents
Page 1
GENERAL DESCRIPTION The DS2431 is a 1024-bit, 1-Wire organized as four memory pages of 256 bits each. Data is written to an 8-byte scratchpad, verified, and then copied to the EEPROM memory special feature, the four memory ...
Page 2
ABSOLUTE MAXIMUM RATINGS I/O Voltage to GND I/O Sink Current Operating Temperature Range Junction Temperature Storage Temperature Range Soldering Temperature Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, ...
Page 3
Note 1: Specifications -40°C are guaranteed by design only and not production-tested. A Note 2: System requirement. Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire ...
Page 4
DESCRIPTION The DS2431 combines 1024 bits of EEPROM, an 8-byte register/control page with user read/write bytes, and a fully-featured 1-Wire interface in a single chip. Each DS2431 has its own 64-bit ROM registration number that is factory ...
Page 5
Figure 2. Hierarchical Structure for 1-Wire Protocol DS2431 Command Level: 1-Wire ROM Function Commands (see Figure 9) DS2431-specific Memory Function Commands (see Figure 7) 64-BIT LASERED ROM Each DS2431 contains a unique ROM code that is 64 bits long. The ...
Page 6
Figure 5. Memory Map ADDRESS RANGE TYPE 0000h to 001Fh R/(W) 0020h to 003Fh R/(W) 0040h to 005Fh R/(W) 0060h to 007Fh R/(W) 1) 0080h R/(W) 1) 0081h R/(W) 1) 0082h R/(W) 1) 0083h R/(W) 1) 0084h R/(W) 0085h R ...
Page 7
The protection control registers determine how incoming data on a write-scratchpad command is loaded into the scratchpad. A protection setting of 55h (Write Protect) causes the incoming data to be ignored and the target address main memory data to be ...
Page 8
WRITING WITH VERIFICATION To write data to the DS2431, the scratchpad has to be used as intermediate storage. First the master issues the Write Scratchpad command to specify the desired target address, followed by the data to be written to ...
Page 9
Figure 7-1. Memory Function Flow Chart DS2431 Increments E2:E0 Bus Master RX “1”s Bus Master TX Memory Function Command 0Fh N Write Scratch- pad ? Y Bus Master TX TA1 (T7:T0), TA2 (T15:T8) DS2431 sets Sets Clears ...
Page 10
Figure 7-2. Memory Function Flow Chart (continued) From Figure Part DS2431 Increments Byte Counter Bus Master RX “1”s To Figure Part AAh N Read Scratch- Pad ? Y Bus Master RX TA1 (T7:T0), TA2 ...
Page 11
Figure 7-3. Memory Function Flow Chart (continued) From Figure Part Copy Scratch- Bus Master TX TA1 (T7:T0), TA2 (T15:T8) and E/S Byte Auth. Code Match ? Bus Master RX “1”s TX Reset ? To Figure 7 nd ...
Page 12
Figure 7-4. Memory Function Flow Chart (continued) From Figure 7 rd F0h 3 Part Read Memory ? Bus Master TX TA1 (T7:T0), TA2 (T15:T8) Address < 90h ? To Figure Part DS2431 sets ...
Page 13
READ SCRATCHPAD COMMAND [AAh] The Read Scratchpad command allows verifying the target address and the integrity of the scratchpad data. After issuing the command code, the master begins reading. The first two bytes are the target address. The next byte ...
Page 14
Figure 8. Hardware Configuration BUS MASTER RX TX Open Drain Port Pin TRANSACTION SEQUENCE The protocol for accessing the DS2431 through the 1-Wire port is as follows: Initialization ROM Function Command Memory Function Command Transaction/Data INITIALIZATION All transactions on the ...
Page 15
SEARCH ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their registration numbers. By taking advantage of the wired-AND property of the bus, the master ...
Page 16
Figure 9-1. ROM Functions Flow Chart From Memory Functions Flow Chart (Figure 7) Bus Master TX ROM Function Command 33h N Read ROM Command ? DS2431 TX Family Code (1 Byte) DS2431 TX Serial Number (6 ...
Page 17
Figure 9-2. ROM Functions Flow Chart (continued Figure 9, 1 Part From Figure 9 st A5h 1 Part Resume Command ? From Figure Part To Figure Part 3Ch ...
Page 18
SIGNALING The DS2431 requires strict protocols to ensure data integrity. The protocol consists of four types of signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write-Zero, Write-One, and Read-Data. Except for the Presence pulse, the ...
Page 19
Master-to-Slave For a write-one time slot, the voltage on the data line must have crossed the V low time t is expired. For a write-zero time slot, the voltage on the data line must stay below the V W1LMAX threshold ...
Page 20
Slave-to-Master A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below V read low time t is expired. During the t RL line low; its internal timing generator determines when this ...
Page 21
CRC GENERATION With the DS2431 there are two different types of CRCs. One CRC is an 8-bit type and is stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the ...
Page 22
COMMAND-SPECIFIC 1-Wire COMMUNICATION PROTOCOL—COLOR CODES Master to slave Slave to master COMMAND-SPECIFIC 1-Wire COMMUNICATION PROTOCOL—LEGEND SYMBOL RST 1-Wire Reset Pulse generated by master. PD 1-Wire Presence Pulse generated by slave. Select Command and data to satisfy the ROM function protocol. ...
Page 23
READ MEMORY (INVALID ADDRESS) RST PD Select RM MEMORY FUNCTION EXAMPLE Write to the first 8 bytes of memory page 1. Read the entire memory. With only a single DS2431 connected to the bus master, the communication looks like this: ...
Page 24
PIN CONFIGURATION (CONTINUED SFN, pinout: Pin 1 ------------- Pin 2 ------------- Side View Bottom View SFN, approx 0.9 mm Package Outline Drawing The SFN package is qualified for electromechanical contact applications only, not for ...