ds2431pt-r Maxim Integrated Products, Inc., ds2431pt-r Datasheet - Page 4

• Manufacturer Part Number: ds2431pt-r
• Description: Ds2431 1024-bit 1-wire Eeprom
• Manufacturer: Maxim Integrated Products, Inc.

DESCRIPTION
The DS2431 combines 1024 bits of EEPROM, an 8-byte register/control page with up to 7 user read/write bytes,
and a fully-featured 1-Wire interface in a single chip. Each DS2431 has its own 64-bit ROM registration number
that is factory lasered into the chip to provide a guaranteed unique identity for absolute traceability. Data is
transferred serially via the 1-Wire protocol, which requires only a single data lead and a ground return. The DS2431
has an additional memory area called the scratchpad that acts as a buffer when writing to the main memory or the
register page. Data is first written to the scratchpad from which it can be read back. After the data has been
verified, a copy scratchpad command transfers the data to its final memory location. Applications of the DS2431
include accessory/PC board identification, medical sensor calibration data storage, analog sensor calibration
including IEEE-P1451.4 Smart Sensors, ink and toner print cartridge identification, and after-market management
of consumables.
OVERVIEW
The block diagram in Figure 1 shows the relationships between the major control and memory sections of the
DS2431. The DS2431 has four main data components: 1) 64-bit lasered ROM, 2) 64-bit scratchpad, 3) four 32-byte
pages of EEPROM, and 4) 64-bit register page. The hierarchical structure of the 1-Wire protocol is shown in Figure
2. The bus master must first provide one of the seven ROM Function Commands, 1) Read ROM, 2) Match ROM, 3)
Search ROM, 4) Skip ROM, 5) Resume, 6) Overdrive-Skip ROM or 7) Overdrive-Match ROM. Upon completion of
an Overdrive ROM command byte executed at standard speed, the device enters Overdrive mode where all
subsequent communication occurs at a higher speed. The protocol required for these ROM function commands is
described in Figure 9. After a ROM function command is successfully executed, the memory functions become
accessible and the master may provide any one of the four memory function commands. The protocol for these
memory function commands is described in Figure 7. All data is read and written least significant bit first.
Figure 1. Block Diagram
I/O
Register Page
Data Memory
256 bits each
Control Unit
4 Pages of
Generator
Function
Memory
CRC16
64 bits
Function Control
1-Wire
4 of 24
PARASITE POWER
Scratchpad
64-bit
Lasered ROM
64-bit
DS2431: 1024-Bit, 1-Wire EEPROM
DS2431