ds2143qn-t-r Maxim Integrated Products, Inc., ds2143qn-t-r Datasheet - Page 31

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ds2143qn-t-r

Manufacturer Part Number
ds2143qn-t-r
Description
Ds2143, Ds2143q E1 Controller
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
DS2143/DS2143Q
13.0 TIMING DIAGRAMS
RECEIVE SIDE TIMING
NOTES:
1. RSYNC in the frame mode (RCR1.6=0).
2. RSYNC in the multiframe mode (RCR1.6=1).
3. RLCLK is programmed to output just the Sa4 bit.
4. RLINK will always output all 5 Sa bits as well as the rest of the receive data stream.
5. This diagram assumes the CAS MF begins with the FAS word.
RECEIVE SIDE 1.544 MHZ BOUNDARY TIMING
(WITH ELASTIC STORE ENABLED)
NOTES:
1. Data from the E1 channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (channel 2 from the E1 link is
mapped to channel 1 of the T1 link, etc.) and the F-bit position is added (forced to 1).
2. RSYNC is in the output mode (RCR1.5=0).
3. RSYNC is in the input mode (RCR1.5=1).
4. RCHBLK is programmed to block channel 24.
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