ds2152 Maxim Integrated Products, Inc., ds2152 Datasheet - Page 56

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ds2152

Manufacturer Part Number
ds2152
Description
Ds2152 Enhanced T1 Single Chip Transceiver
Manufacturer
Maxim Integrated Products, Inc.
Datasheet

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DS2152
11.3 Minimum Delay Synchronous RSYSCLK/TSYSCLK Mode
In applications where the DS2152 is connected to backplanes that are frequency-locked to the recovered
T1 clock (i.e., the RCLK output), the full two-frame depth of the on-board elastic stores is really not
needed. In fact, in some delay-sensitive applications the normal two-frame depth may be excessive. If the
CCR3.7 bit is set to 1, then the receive elastic store (and also the transmit elastic store if it is enabled) will
be forced to a maximum depth of 32 bits instead of the normal 386 bits. In this mode, RSYSCLK and
TSYSCLK must be tied together and they must be frequency-locked to RCLK. All the slip contention
logic in the DS2152 is disabled (since slips cannot occur). Also, since the buffer depth is no longer two
frames deep, the DS2152 must be set up to source a frame pulse at the RSYNC pin and this output must
be tied to the TSSYNC input. On power-up after the RSYSCLK and TSYSCLK signals have locked to
the RCLK signal, the elastic store reset bit (CCR3.6) should be toggled from 0 to 1 to ensure proper
operation.
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