upd78f0114m6gb-8es Renesas Electronics Corporation., upd78f0114m6gb-8es Datasheet - Page 517

• Manufacturer Part Number: upd78f0114m6gb-8es
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

Watch
timer
Watchdog
timer
A/D
converter
Function
WTM: Watch
timer operation
mode register
Interrupt
request
WDTM:
Watchdog timer
mode register
WDTE:
Watchdog timer
enable register
When “Ring-
OSC cannot be
stopped” is
selected by
mask option
When “Ring-OSC
can be stopped
by software” is
selected by mask
option
ADM: A/D
converter mode
register
Details of
Function
Do not change the count clock and interval time (by setting bits 4 to 7 (WTM4 to
WTM7) of WTM) during watch timer operation.
When operation of the watch timer and 5-bit counter is enabled by the watch timer
mode control register (WTM) (by setting bits 0 (WTM0) and 1 (WTM1) of WTM to
1), the interval until the first interrupt request (INTWT) is generated after the
register is set does not exactly match the specification made with bits 2 and 3
(WTM2, WTM3) of WTM. Subsequently, however, the INTWT signal is generated
at the specified intervals.
If data is written to WDTM, a wait cycle is generated. Do not write data to WDTM
when the CPU is operating on the subsystem clock and the X1 input clock is
stopped. For details, see CHAPTER 31 CAUTIONS FOR WAIT.
Set bits 7, 6, and 5 to 0, 1, and 1, respectively (when “Ring-OSC cannot be
stopped” is selected by a mask option, other values are ignored).
After reset is released, WDTM can be written only once by an 8-bit memory
manipulation instruction. If writing is attempted a second time, an internal reset
signal is generated. If the source clock to the watchdog timer is stopped,
however, an internal reset signal is generated when the source clock to the
watchdog timer resumes operation.
WDTM cannot be set by a 1-bit memory manipulation instruction.
If “Ring-OSC can be stopped by software” is selected by the mask option and the
watchdog timer is stopped by setting WDCS4 to 1, the watchdog timer does not
resume operation even if WDCS4 is cleared to 0. In addition, the internal reset
signal is not generated.
If a value other than ACH is written to WDTE, an internal reset signal is generated.
If the source clock to the watchdog timer is stopped, however, an internal reset
signal is generated when the source clock to the watchdog timer resumes
operation.
If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset
signal is generated. If the source clock to the watchdog timer is stopped,
however, an internal reset signal is generated when the source clock to the
watchdog timer resumes operation.
The value read from WDTE is 9AH (this differs from the written value (ACH)).
In this mode, operation of the watchdog timer absolutely cannot be stopped even
during STOP instruction execution. For 8-bit timer H1 (TMH1), a division of the
Ring-OSC can be selected as the count source, so clear the watchdog timer using
the interrupt request of TMH1 before the watchdog timer overflows after STOP
instruction execution. If this processing is not performed, an internal reset signal
is generated when the watchdog timer overflows after STOP instruction execution.
In this mode, watchdog timer operation is stopped during HALT/STOP instruction
execution. After HALT/STOP mode is released, counting is started again using
the operation clock of the watchdog timer set before HALT/STOP instruction
execution by WDTM. At this time, the counter is not cleared to 0 but holds its
value.
A/D conversion must be stopped before rewriting bits FR0 to FR2 to values other
than the identical data.
For the sampling time of the A/D converter and the A/D conversion start delay
time, see (11) in 11.6 Cautions for A/D Converter.
If data is written to ADM, a wait cycle is generated. Do not write data to ADM
when the CPU is operating on the subsystem clock and the X1 input clock is
stopped. For details, see CHAPTER 31 CAUTIONS FOR WAIT.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16227EJ3V0UD
Cautions
p. 209
p. 212
p. 217
p. 217
p. 217
p. 217
p. 217
p. 218
p. 218
p. 218
p. 219
p. 220
p. 228
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