upd78f0114m6gb-8es Renesas Electronics Corporation., upd78f0114m6gb-8es Datasheet - Page 526

• Manufacturer Part Number: upd78f0114m6gb-8es
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

526
Standby
function
Reset
function
Function
OSTC:
Oscillation
stabilization
time counter
status register
OSTS:
Oscillation
stabilization
time select
register
STOP mode
setting and
operation status
LVI circuit reset An LVI circuit internal reset does not reset the LVI circuit.
Reset timing
due to
watchdog timer
overflow
RESF: Reset
control flag
register
Details of
Function
−
After the above time has elapsed, the bits are set to 1 in order from MOST11 and
remain 1.
If the STOP mode is entered and then released while the Ring-OSC clock is being
used as the CPU clock, set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by
The X1 oscillation stabilization time counter counts only during the oscillation
stabilization time set by OSTS. Therefore, note that only the statuses during the
oscillation stabilization time set by OSTS are set to OSTC after STOP mode has
been released.
The wait time when STOP mode is released does not include the time after STOP
mode release until clock oscillation starts (“a” below) regardless of whether STOP
mode is released by RESET input or interrupt generation.
If the STOP mode is entered and then released while the Ring-OSC clock is being
used as the CPU clock, set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by
The X1 oscillation stabilization time counter counts only during the oscillation
stabilization time set by OSTS. Therefore, note that only the statuses during the
oscillation stabilization time set by OSTS are set to OSTC after STOP mode has
been released.
The wait time when STOP mode is released does not include the time after STOP
mode release until clock oscillation starts (“a” below) regardless of whether STOP
mode is released by RESET input or interrupt generation.
To set the STOP mode while the X1 input clock is the CPU clock, set OSTS
before executing the STOP instruction.
Set OSTS after confirming that the oscillation stabilization time expected by OSTS
has elapsed.
Because the interrupt request signal is used to clear the standby mode, if there is
an interrupt source with the interrupt request flag set and the interrupt mask flag
reset, the standby mode is immediately cleared if set. Thus, the STOP mode is
reset to the HALT mode immediately after execution of the STOP instruction and
the system returns to the operating mode as soon as the wait time set using the
oscillation stabilization time select register (OSTS) has elapsed.
For an external reset, input a low level for 10
During reset input, the X1 input clock and Ring-OSC clock stop oscillating.
When the STOP mode is released by a reset, the STOP mode contents are held
during reset input. However, the port pins become high-impedance, except for
P130, which is set to low-level output.
A watchdog timer internal reset resets the watchdog timer.
Do not read data by a 1-bit memory manipulation instruction.
OSTS
OSTS
APPENDIX D LIST OF CAUTIONS
User’s Manual U16227EJ3V0UD
Cautions
µ
s or more to the RESET pin.
p. 339
p. 339
p. 339
p. 340
p. 340
p. 340
p. 340
p. 346
p. 350
p. 350
p. 350
p. 351
p. 352
p. 356
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