upd78f0148m1gka1-9eu Renesas Electronics Corporation., upd78f0148m1gka1-9eu Datasheet - Page 641

• Manufacturer Part Number: upd78f0148m1gka1-9eu
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

Main
clock
X1
oscillator,
subsystem
clock
oscillator
Prescaler
Internal
oscillator
CPU
clock
16-bit
timer/
event
counters
00, 01
(TM00,
TM01)
Function
OSTS:
Oscillation
stabilization
time select
register
CR00n: 16-bit
timer capture/
compare
register 00n
Details of
Function
−
−
−
−
If the STOP mode is entered and then released while the internal oscillation clock
is being used as the CPU clock, set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set
The X1 oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. Note, therefore, that only the status up to the
oscillation stabilization time set by OSTS is set to OSTC after STOP mode is
released.
The wait time when STOP mode is released does not include the time after STOP
mode release until clock oscillation starts (“a” below) regardless of whether STOP
mode is released by RESET input or interrupt generation.
When using the X1 oscillator and subsystem clock oscillator, wire as follows in the
area enclosed by the broken lines in Figures 6-8 and 6-9 to avoid an adverse
effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating
• Always make the ground point of the oscillator capacitor the same potential as
• Do not fetch signals from the oscillator.
Note that the subsystem clock oscillator is designed as a low-amplitude circuit for
reducing power consumption.
When the internal oscillation clock is selected as the clock supplied to the CPU,
the prescaler generates various clocks by dividing the internal oscillator output (f
= 240 kHz (TYP.)).
The RSTOP setting is valid only when “Can be stopped by software” is set for
internal oscillator by a mask option.
To calculate the maximum time, set f
Selection of the CPU clock cycle division factor (PCC0 to PCC2) and switchover
from the X1 input clock to the subsystem clock (changing CSS from 0 to 1) should
not be set simultaneously.
Simultaneous setting is possible, however, for selection of the CPU clock cycle
division factor (PCC0 to PCC2) and switchover from the subsystem clock to the
X1 input clock (changing CSS from 1 to 0).
Setting the following values is prohibited when the CPU operates on the internal
oscillation clock.
• CSS, PCC2, PCC1, PCC0 = 0, 0, 0, 1 (settable only for standard products and
• CSS, PCC2, PCC1, PCC0 = 0, 0, 1, 0
• CSS, PCC2, PCC1, PCC0 = 0, 0, 1, 1
• CSS, PCC2, PCC1, PCC0 = 0, 1, 0, 0
Set a value other than 0000H to CR00n in the mode in which clear & start occurs
on a match of TM0n and CR00n.
If CR00n is set to 0000H in the free-running mode and in the clear mode using the
valid edge of the TI00n pin, an interrupt request (INTTM00n) is generated when
the value of CR00n changes from 0000H to 0001H following TM0n overflow
(FFFFH). Moreover, INTTM00n is generated after a match of TM0n and CR00n is
detected, a valid edge of the TI01n pin is detected, or the timer is cleared by a
one-shot trigger.
When the valid edge of the TI01n pin is used, P01 or P06 cannot be used as the
timer output (TO0n) pin. Moreover, when the TO0n pin is used, the valid edge of
the TI01n pin cannot be used.
current flows.
V
current flows.
by OSTS
(A) grade products)
SS
. Do not ground the capacitor to a ground pattern through which a high
APPENDIX D LIST OF CAUTIONS
User’s Manual U15947EJ3V1UD
Cautions
R
= 120 kHz.
X
p. 138
p. 138
p. 140
p. 142
p. 149
p. 150
p. 151
p. 151
p. 161
p. 161
p. 161
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