mrf89xa Microchip Technology Inc., mrf89xa Datasheet - Page 28

• Manufacturer Part Number: mrf89xa
• Description: Ultra-low Power, Integrated Ism Band Sub-ghz Transceiver
• Manufacturer: Microchip Technology Inc.

2.12
In Buffered and Packet modes of operation, data to be
transmitted and data that has been received are stored
in a configurable First In First Out (FIFO) buffer. The
FIFO is accessed through the SPI data interface and
provides several interrupts for transfer management.
The FIFO is 1 byte (8 bits) wide; therefore, it only
performs byte (parallel) operations, whereas the
demodulator functions serially. A shift register (SR) is
therefore employed to interface the demodulator and
the FIFO. In Transmit mode it takes bytes from the
FIFO and outputs them serially (MSB first) at the
programmed bit rate to the modulator. Similarly, in
Receive mode the shift register gets bit-by-bit data from
the demodulator and writes them byte-by-byte to the
FIFO. This is illustrated in Figure 2-16.
FIGURE 2-16:
FIGURE 2-17:
DS70622B-page 28
MRF89XA
Data TX/RX
FIFO and Shift Register (SR)
1
0x00
0x1F
MSB
FIFO AND SHIFT
REGISTER
MRF89XA MEMORY SPACE
SR (8 bits)
Byte 0
Byte 1
Control Registers
8
Data TX/RX
LSB
FIFO
1
Preliminary
0x40
0x00
MSB
2.13
The memory in the MRF89XA transceiver is
implemented as static RAM and is accessible through
the SPI port. The memory configuration of the
MRF89XA is illustrated in Figure 2-17 and Figure 2-18.
SHIFT REGISTER
Transmit/Receive
MRF89XAConfiguration/Control/
Status Registers
(8 bits)
FIFO
© 2010 Microchip Technology Inc.
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