74LVC109PW,112 NXP Semiconductors, 74LVC109PW,112 Datasheet - Page 10

• Manufacturer Part Number: 74LVC109PW,112
• Description: IC DUAL JK F-F POS-EDGE 16TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVCr
• Type: JK Typer

Specifications of 74LVC109PW,112

• Output Type: Differential
• Package / Case: 16-TSSOP
• Function: Set(Preset) and Reset
• Number Of Elements: 2
• Number Of Bits Per Element: 1
• Frequency - Clock: 150MHz
• Trigger Type: Positive Edge
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Logic Family: LVC
• Logic Type: J-K Positive Edge Triggered Flip Flop
• Polarity: Inverting/Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 4 ns at 3.3 V
• High Level Output Current: - 24 mA
• Low Level Output Current: 24 mA
• Supply Voltage (max): 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 1.2 V
• Technology: CMOS
• Number Of Bits: 2
• Number Of Elements: 2
• Clock-edge Trigger Type: Positive-Edge
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Package Type: TSSOP
• Frequency (max): 225MHz
• Operating Supply Voltage (min): 1.2V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time - Propagation: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 74LVC109PW; 74LVC109PW; 935191070112

Philips Semiconductors
Notes
1. All typical values are measured at T
2. These typical values are measured at V
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed
2004 Mar 18
SYMBOL
T
t
t
t
t
t
t
t
f
t
PHL
PLH
PHL
W
rem
su
h
max
sk(0)
amb
Dual JK flip-flop with set and reset;
positive-edge trigger
by design.
/t
PLH
= 40 to 125 C
propagation delay nCP to nQ and
nCP to nQ
propagation delay nSD to nQ and
nRD to nQ
propagation delay nSD to nQ and
nRD to nQ
clock pulse width HIGH or LOW
set or reset pulse width HIGH or
LOW
removal time nSD, nRD to nCP
set-up time nJ and nK to CP
hold time nJ and nK to nCP
maximum clock pulse frequency
skew
PARAMETER
amb
= 25 C.
CC
= 3.3 V.
see Figs 6 and 8 2.7
see Figs 7 and 8 2.7
see Figs 7 and 8 2.7
see Fig. 6
see Fig. 7
see Fig. 7
see Fig. 6
see Fig. 6
see Fig. 6
note 3
WAVEFORMS
TEST CONDITIONS
10
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
V
CC
(V)
1.5
1.0
1.5
1.0
1.5
1.0
3.3
3.0
3.0
2.5
2.0
150
MIN.
TYP.
Product specification
74LVC109
9.5
8.5
10.5
9.0
9.0
8.5
1.5
MAX.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
UNIT