74LVC16374ADGG,118 NXP Semiconductors, 74LVC16374ADGG,118 Datasheet - Page 13

• Manufacturer Part Number: 74LVC16374ADGG,118
• Description: IC 16BIT EDGE TRIG D FF 48TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVCr
• Type: D-Type Busr

Specifications of 74LVC16374ADGG,118

• Package / Case: 48-TSSOP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Output Type: Tri-State Non Inverted
• Function: Standard
• Current - Output High, Low: 24mA, 24mA
• Number Of Elements: 2
• Number Of Bits Per Element: 8
• Delay Time - Propagation: 7ns
• Frequency - Clock: 100MHz
• Trigger Type: Positive Edge
• Number Of Circuits: 2
• Logic Family: LVC
• Logic Type: CMOS
• Polarity: Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 14 ns
• High Level Output Current: - 24 mA
• Supply Voltage (max): 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 1.2 V
• Technology: CMOS
• Number Of Bits: 16
• Number Of Elements: 2
• Clock-edge Trigger Type: Positive-Edge
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Low Level Output Current: 24mA
• Operating Supply Voltage (min): 1.2V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935235190118

NXP Semiconductors
12. Package outline
Fig 11. Package outline SOT370-1 (SSOP48)
74LVC_LVCH16374A_7
Product data sheet
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
UNIT
mm
VERSION
OUTLINE
SOT370-1
48
max.
1
2.8
Z
A
y
0.4
0.2
A
1
pin 1 index
2.35
2.20
A
2
IEC
e
0.25
A
3
D
0.3
0.2
b
p
All information provided in this document is subject to legal disclaimers.
0.22
0.13
MO-118
JEDEC
c
0
16.00
15.75
REFERENCES
D
Rev. 07 — 23 March 2010
(1)
74LVC16374A; 74LVCH16374A
E
7.6
7.4
b
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
(1)
p
JEITA
25
24
scale
0.635
5
e
w
M
10.4
10.1
H
c
E
1.4
L
A
10 mm
2
A
1.0
0.6
L
1
p
1.2
1.0
Q
H
E
E
detail X
PROJECTION
EUROPEAN
0.25
v
L
L
Q
p
0.18
w
(A )
3
A
0.1
© NXP B.V. 2010. All rights reserved.
y
θ
A
ISSUE DATE
99-12-27
03-02-19
X
0.85
0.40
Z
v
(1)
M
SOT370-1
A
8
0
θ
o
o
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