si5318 ETC-unknow, si5318 Datasheet - Page 15

• Manufacturer Part Number: si5318
• Description: Sonet/sdh Precision Clock Multiplier
• Manufacturer: ETC-unknow

Output Clock Frequency
Range
Reserved
155 MHz
19 MHz
Driver Powerdown
Input Clock
Frequency
Range
Reserved
Reserved
Reserved
155 MHz
78 MHz
39 MHz
19 MHz
Reserved
*Note: When DBLBW = 1, FXDDELAY must be asserted.
Bandwidth
Table 9. Nominal Clock Output Frequencies
12800 Hz
Table 8. Nominal Clock Input Frequencies
6400 Hz
6400 Hz
3200 Hz
3200 Hz
1600 Hz
1600 Hz
800 Hz
Loop
Table 7. Loop Bandwidth Settings
INFRQSEL2 INFRQSEL1 INFRQSEL0
BWSEL1
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
BWSEL0
FRQSEL1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
DBLBW
FRQSEL0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
*
Rev. 1.0
2.3. PLL Performance
The Si5318 PLL is designed to provide extremely low
jitter generation, high jitter tolerance, and a well-
controlled jitter transfer function with low peaking and a
high degree of jitter attenuation.
2.3.1. Jitter Generation
Jitter generation is defined as the amount of jitter
produced at the output of the device with a jitter free
input clock. Generated jitter arises from sources within
the VCO and other PLL components. Jitter generation is
also a function of the PLL bandwidth setting. Higher
loop bandwidth settings may result in lower jitter
generation, but may also result in less attenuation of
jitter on the input clock signal.
2.3.2. Jitter Transfer
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter for a specified jitter frequency. The
jitter transfer characteristic determines the amount of
input clock jitter that passes to the outputs. The DSPLL
technology used in the Si5318 provides tightly-
controlled jitter transfer curves because the PLL gain
parameters are determined by digital circuits that do not
vary over supply voltage, process, and temperature. In
a system application, a well-controlled transfer curve
minimizes the output clock jitter variation from board to
board, providing more consistent system level jitter
performance.
The jitter transfer characteristic is a function of the
BWSEL[1:0] setting. (See Table 7.) Lower bandwidth
selection settings result in more jitter attenuation of the
incoming clock but may result in higher jitter generation.
Table 4 on page 8 gives the 3 dB bandwidth and
peaking values for specified BWSEL settings. Figure 6
shows the jitter transfer curve mask.
Jitter Out
Jitter In
Figure 6. PLL Jitter Transfer Mask/Template
Transfer
Jitter
0 dB
(s)
Peaking
F
BW
–20 dB/dec.
Si5318
f
Jitter
15