si5318 ETC-unknow, si5318 Datasheet - Page 25

• Manufacturer Part Number: si5318
• Description: Sonet/sdh Precision Clock Multiplier
• Manufacturer: ETC-unknow

*Note: The LVTLL inputs on the Si5318 device have an internal pulldown mechanism that causes these inputs to default to a
A4–8, B5, B8
C2, D3–D5,
D6, D7, E6,
C3–C7, E2,
F2, G2–G8
E7, F3–F7
E3–E5
Pin #
H2
D2
logic low state if the input is not driven from an external source.
RSVD_NC
Pin Name
DBLBW
V
V
REXT
GND
DD33
DD25
Table 10. Si5318 Pin Descriptions (Continued)
GND
V
V
I/O
—
I*
DD
DD
I
Signal Level
Analog
Supply
Supply
Supply
LVTTL
LVTTL
Rev. 1.0
Reserved—No Connect.
This pin must be left unconnected for normal
operation.
3.3 V Supply.
3.3 V power is applied to the V
supply bypassing/decoupling for this configuration is
indicated in the typical application diagram for 3.3 V
supply operation.
2.5 V Supply.
These pins provide a means of connecting the
compensation network for the on-chip regulator.
Ground.
Must be connected to system ground. Minimize the
ground path impedance for optimal performance of
the device.
External Biasing Resistor.
Used by on-chip circuitry to establish bias currents
within the device. This pin must be connected to
GND through a 10 kΩ (1%) resistor.
Double Bandwidth
Active high input to boost the selected bandwidth 2x.
When this pin is high, the loop filter bandwidth
selected on BWSEL[1:0] is doubled. When this pin is
high, FXDDELAY must also be high.
Description
DD33
pins. Typical
Si5318
25