si3019-x-fs Silicon Laboratories, si3019-x-fs Datasheet - Page 12
si3019-x-fs
Manufacturer Part Number
si3019-x-fs
Description
Global Serial Interface Direct Access Arrangement
Manufacturer
Silicon Laboratories
Datasheet
1.SI3019-X-FS.pdf
(94 pages)
- Current page: 12 of 94
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Si3018/19/10
Table 8. Switching Characteristics—Serial Interface (Master Mode, DCE = 1, FSD = 0)
(V
12
Parameter
Cycle Time, SCLK
SCLK Duty Cycle
Delay Time, SCLK ↑ to FSYNC ↑
Delay Time, SCLK ↑ to FSYNC ↓
Delay Time, SCLK ↑ to SDO valid
Delay Time, SCLK ↑ to SDO Hi-Z
Delay Time, SCLK ↑ to FSD ↓
Delay Time, SCLK ↑ to FSD ↑
Setup Time, SDO Before SCLK ↓
Hold Time, SDO After SCLK ↓
Notes:
A
= Charge Pump, V
1. All timing is referenced to the 50% level of the waveform. Input test levels are V
2. See "5.27.Multiple Device Support" on page 38 for functional details.
(mode 1)
(Mode 0)
(Mode 1)
(mode 0)
(slave 1)
(master)
FSYNC
FSYNC
FSYNC
FSYNC
SCLK
SDO
SDO
1,2
SDI
t
d1
D
Figure 4. Serial Interface Timing Diagram (DCE = 1, FSD = 0)
= 3.0 to 3.6 V, T
t
c
t
d3
D15
t
D15
d2
t
d2
t
su
t
su
A
= 0 to 70 °C, C
D14
D14
t
16 SCLKs
t
h
Symbol
h
D13
t
t
t
t
t
t
t
t
D13
dty
t
t
d1
d2
d3
d4
d5
d6
su
h
c
L
Rev. 1.05
= 20 pF)
32 SCLKs
Min
244
25
20
—
—
—
—
—
—
—
D0
D0
t
t
d6
d4
1/256 Fs
Typ
50
—
—
—
—
—
—
—
—
16 SCLKs
IH
= V
D
– 0.4 V, V
Max
20
20
20
20
20
20
—
—
—
—
IL
= 0.4 V.
t
D15
t
t
d2
d3
d5
t
t
d2
d5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
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