si3019-x-fs Silicon Laboratories, si3019-x-fs Datasheet - Page 13
si3019-x-fs
Manufacturer Part Number
si3019-x-fs
Description
Global Serial Interface Direct Access Arrangement
Manufacturer
Silicon Laboratories
Datasheet
1.SI3019-X-FS.pdf
(94 pages)
- Current page: 13 of 94
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Table 9. Switching Characteristics—Serial Interface (Master Mode, DCE = 1, FSD = 1)
(V
Parameter
Cycle Time, SCLK
SCLK Duty Cycle
Delay Time, SCLK ↑ to FSYNC ↑
Delay Time, SCLK ↑ to FSYNC ↓
Delay Time, SCLK ↑ to SDO Valid
Delay Time, SCLK ↑ to SDO Hi-Z
Delay Time, SCLK ↑ to FSD ↓
Setup Time, SDO Before SCLK ↓
Hold Time, SDO After SCLK ↓
Notes:
D
(mode 1)
(slave 1)
(master)
= 3.0 to 3.6 V, T
1. All timing is referenced to the 50% level of the waveform. Input test levels are V
2. See "5.27.Multiple Device Support" on page 38 for functional details.
FSYNC
SCLK
SDO
SDO
FSD
SDI
1, 2
t
d1
A
=
0 to 70 °C, C
Figure 5. Serial Interface Timing Diagram (DCE = 1, FSD = 1)
t
c
t
d3
L
= 20 pF)
t
d2
D15
D15
t
su
Symbol
t
su
t
t
t
t
t
t
t
dty
t
t
d1
d2
d3
d4
d5
su
D14
h
c
D14
Rev. 1.05
t
h
t
h
D13
Min
244
25
20
—
—
—
—
—
—
1/256 Fs
D1
Typ
50
—
—
—
—
—
—
—
IH
= V
D
Si3018/19/10
– 0.4 V, V
D0
D0
Max
20
20
20
20
20
—
—
—
—
IL
= 0.4 V.
t
t
d3
d4
t
d5
D15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
%
13
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