si4420 Silicon Laboratories, si4420 Datasheet - Page 17

• Manufacturer Part Number: si4420
• Description: Si4420 Universal Ism Band Fsk Transceiver
• Manufacturer: Silicon Laboratories

Bits 2-0 (f2 to f0): DQD threshold parameter.
7. FIFO and Reset Mode Command
Bits 7-4 (f3 to f0): FIFO IT level. The FIFO generates IT when the number of received data bits reaches this level.
Bit 2 (al): Set the input of the FIFO fill start condition:
Note: Synchron pattern in microcontroller mode is 2DD4h.
Bit 1 (ff): FIFO fill will be enabled after synchron pattern reception. The FIFO fill stops when this bit is cleared.
Bit 0 (dr): Disables the highly sensitive RESET mode. If this bit is cleared, a 600 mV glitch in the power supply may cause a system reset. For
more detailed description see the Reset modes section.
Note:
Bit
To restart the synchron pattern recognition, bit 1 should be cleared and set.
15
1
Note: To let the DQD report "good signal quality" the threshold parameter should be less than 4 in the case when the bitrate is
14
SYNCHRON
1
PATTERN
close to the deviation. At higher deviation/bitrate settings higher threshold parameter can report "good signal quality" as
well.
13
0
12
0
11
1
10
0
FFIT
er**
FFOV
9
1
al
0
1
8
0
f3
7
Note:
* For details see the Configuration Setting Command
** For deatils see the Power Management Command
Synchron pattern
ef*
Always fill
al
f2
ff
6
f1
5
f0
4
3
0
FIFO_WRITE _EN
nFIFO_RESET
al
2
FIFO_LOGIC
1
ff
dr
0
CA80h
POR
Si4420
17