scc2681t NXP Semiconductors, scc2681t Datasheet - Page 8

• Manufacturer Part Number: scc2681t
• Description: Dual Asynchronous Receiver/transmitter Duart
• Manufacturer: NXP Semiconductors

1. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and V
2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4 V and 2.4 V with a
3. Typical values are at +25 C, typical supply voltages, and typical processing parameters.
Philips Semiconductors
AC ELECTRICAL CHARACTERISTICS
NOTES:
2004 Apr 06
Reset timing (see Figure 3)
Bus timing (see Figure 4) (Note 5)
Port timing (see Figure 5)
Interrupt timing (see Figure 6)
Clock timing (see Figure 7)
Transmit timing (see Figure 8)
Receive timing (see Figure )
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
f
t
f
f
t
f
t
t
t
t
SYMBOL
SYMBOL
RES
AVEL
ELAX
RLRH
EHEL
RLDA
RLDV
RHDI
RHDF
WLWH
DVWH
WHDI
PS
PH
PD
IR
CLK
CLK
CTC
CTC
RX
RX
TX
TX
TXD
TCS
RXS
RXH
Dual asynchronous receiver/transmitter (DUART)
supply range.
transition time of 20 ns maximum. For X1/CLK this swing is between 0.4 V and 4.0 V. All time measurements are referenced at input
voltages of 0.8 V and 2.0 V and output voltages of 0.8 V and 2.0 V as appropriate.
Reset pulse width
A0–A3 set-up to RDN and CEN, or WRN and CEN LOW
RDN and CEN, or WRN and CEN LOW to A0–A3 invalid
RDN and CEN LOW to RDN or CEN HIGH
CEN HIGH to CEN LOW
CEN and RDN LOW to data outputs active
CEN and RDN LOW to data valid
CEN or RDN HIGH to data invalid
CEN or RDN HIGH to data outputs floating
WRN and CEN LOW to WRN or CEN HIGH
Data input valid to WRN or CEN HIGH
WRN or CEN HIGH to data invalid
Port input set-up time before RDN LOW
Port input hold time after RDN HIGH
Port output valid after WRN HIGH
INTRN (or OP3–OP7 when used as interrupts) negated from:
X1/CLK HIGH or LOW time
X1/CLK frequency
CTCLK (IP2) HIGH or LOW time
CTCLK (IP2) frequency
RxC HIGH or LOW time
RxC frequency
TxC HIGH or LOW time
TxC frequency
TxD output delay from TxC external clock input on IP pin
Output delay from TxC LOW at OP pin to TxD data output
RxD data set-up time before RxC HIGH at external clock input on IP pin
RxD data hold time after RxC HIGH at external clock input on IP pin
Read RHR (RxRDY/FFULL interrupt)
Write THR (TxRDY interrupt)
Reset command (delta break interrupt)
Stop C/T command (counter interrupt)
Read IPCR (input port change interrupt)
Write IMR (clear of interrupt mask bit)
8
(16 )
(1 )
(16 )
(1 )
6, 7
8
8
PARAMETER
PARAMETER
8
8
1, 2, 3, 4
8
Min
100
120
110
110
200
1.0
15
10
75
35
15
90
55
55
25
0
–
–
0
0
–
–
–
–
–
–
–
2
0
0
0
0
0
–
0
LIMITS
3.6864
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max
100
200
200
200
200
200
200
200
300
100
SCC2681T
65
–
–
–
–
–
–
–
–
–
–
–
–
4
8
8
1
4
1
–
–
Product data
UNIT
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
CC