scc2681t NXP Semiconductors, scc2681t Datasheet - Page 9

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scc2681t

Manufacturer Part Number
scc2681t
Description
Dual Asynchronous Receiver/transmitter Duart
Manufacturer
NXP Semiconductors
Datasheet

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5. For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle
6. If CEN is used as the ‘strobing’ input, the parameter defines the minimum HIGH times between one CEN and the next. The RDN signal must
4. Test conditions for outputs: C
7. Consecutive write operations to the same command register require at least three edges of the X1 clock between writes.
8. Minimum frequencies are not tested but are guaranteed by design.
Philips Semiconductors
2004 Apr 06
Dual asynchronous receiver/transmitter (DUART)
and the signal negated first terminates the cycle.
be negated for t
RDN input even if the CEN is used as the strobing signal for bus operations.
(WRITE)
(WRITE)
(READ)
(READ)
A0–A3
D0–D7
D0–D7
WRN
RDN
CEN
CEN
EHEL
t
AVEL
FLOAT
to guarantee that any status register changes are valid. As a consequence, this minimum time must be met for the
t
RLDA
L
= 150 pF, except interrupt outputs. Test conditions for interrupt outputs: C
RESET
t
ELAX
t
RLDV
t
WLWH
INVALID
t
RLRH
t
DVWH
VALID
Figure 3. Reset Timing
Figure 4. Bus Timing
t
RES
VALID
9
t
WHDI
t
t
EHEL
RHDI
t
RHDF
SD00028
t
EHEL
L
= 50 pF, R
FLOAT
L
= 2.7 k to V
SCC2681T
SD00100
Product data
CC
.

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