isl3873 Intersil Corporation, isl3873 Datasheet - Page 16

• Manufacturer Part Number: isl3873
• Description: Wireless Lan Integrated Medium Access Controller With Baseband Processor
• Manufacturer: Intersil Corporation

Master Clock
Prescaler
The ISL3873 contains a clock prescaler to provide flexibility in
the choice of clock input frequencies. For 11Mb/s operation, the
internal master clock, MCLK, must be between 11MHz and
16MHz. The clock generator itself requires an input from the
prescaler that is twice the desired MCLK frequency. Thus the
lowest oscillator frequency that can be used for an 11MHz
MCLK is 22MHz. The prescaler can divide by integers and 1/2
steps (IE 1, 1.5, 2, 2.5). Another way to look at it is that the
divisor ratio between the external clock source and the internal
MCLK may be integers between 2 and 14.
Typically, the 44MHz baseband clock is used as the input, and
the prescaler is set to divide by 2. Another useful configuration
is to set the prescaler to divide by 1.5 (resulting in 44MHz 3)
for an MCLK of 14.67MHz. Contact the factory for further
details on setting the clock prescaler register in the ISL3873.
Low-Frequency Crystal
The ISL3873 MAC controller can accept the same clock signal
as the PHY baseband processor (typically 44MHz), thereby
avoiding the need for a separate, MAC-specific oscillator. The
ISL3873 input has a low-frequency oscillator. This low-
frequency oscillator is intended for use with a 32.768KHz,
Power Down State
Receive State
Transmit State
PLL Active State
PLL Disable State
PLL_PE is controlled via the serial interface, and can be used to
disable the internal synthesizer, the actual synthesizer control is
an AND function of PLL_PE, and a result of the OR function of
PE1 and PE2. PE1 and PE2 will directly control the power enable
functionality of the LO buffer(s)/phase shifter.
TR_SW_BAR
TABLE 2. POWER ENABLE STATES
PA_PE
TR_SW
PE1
PE2
PE1
16
X
0
1
1
0
FIGURE 10. TRANSMIT CONTROL SIGNAL SEQUENCING
PE2
X
0
1
0
1
PLL_PE
1
1
1
1
0
t
D1
ISL3873
t
D3
tuning-fork type watch crystal to permit accurate timekeeping
with very low power consumption during sleep state.
If a 32.768KHz crystal is connected, the resulting LF clock is
supplied to an interval timer to permit measuring sleep
intervals as well as providing a programmable wake-up time.
In addition, the clock generator can operate either from CLKIN
or (very slowly) from the LF clock. Glitch-free switching
between these two clock sources, under firmware control, is
provided by two, non-architectural Strobe functions (“FAST”
and “SLOW”). In addition, during hardware reset, the clock
generator source is set to the LF clock if no edges are
detected on CLKIN for two cycles of the LF clock (roughly 61
microseconds). This allows proper initialization with omission
of either clock source, since without the LF crystal attached
there will not be cycles of the LF clock to activate the detection
circuit. The ability to initialize the ISL3873 using the LF
oscillator to generate MCLK allows the high-frequency (PHY)
oscillator to be powered down during sleep state. If this is
done, firmware can turn on power to the PHY oscillator upon
wake-up, and use the interval timer to measure the start-up
and stabilization period before switching to use CLKIN.
Clock Generator
The ISL3873 can operate with MCLK frequencies up to at least
25MHz and CLKIN frequencies of at least 50MHz. The MCLK
prescaler generates MCLK (and QCLK) from the external clock
provided at the CLKIN input, or from the output of the LF
oscillator. The MCLK prescaler divides the selected input clock
by any integer value between 2 and 16, inclusive.
• When using a 44MHz CLKIN, as is typical for 802.11 or
• When using a 48MHz CLKIN, as is typical for 802.11 or
The MCLK prescaler is set to divide by 16 at hardware reset
to allow initialization firmware to be executed from slow
802.11b controllers with a PC Card Host Interface, common
divisors are 3 (14.67MHz), 4 (11MHz), or 5 (8.8MHz)
802.11b controllers with a USB host interface, common
divisors are 3 (16MHz), 4 (12MHz), or 6 (8MHz)
t
t
D5
D4