isl3873 Intersil Corporation, isl3873 Datasheet - Page 19

• Manufacturer Part Number: isl3873
• Description: Wireless Lan Integrated Medium Access Controller With Baseband Processor
• Manufacturer: Intersil Corporation

achieve initial Pseudo Noise (PN) synchronization while the
header includes the necessary data fields of the
communications protocol to establish the physical layer link.
The transmitter generates the synchronization preamble and
header and knows when to make the DBPSK to DQPSK or
CCK switchover, as required.
For the 1 and 2Mbps modes, the transmitter accepts data
from the external source, scrambles it, differentially encodes
it as either DBPSK or DQPSK, and spreads it with the BPSK
PN sequence. The baseband digital signals are then output
to the external IF modulator.
For the CCK modes, the transmitter inputs the data and
partitions it into nibbles (4 bits) or bytes (8 bits). At 5.5Mbps,
it uses two of those bits to select one of 4 complex spread
sequences from a table of CCK sequences and then QPSK
modulates that symbol with the remaining 2 bits. Thus, there
are 4 possible spread sequences to send at four possible
carrier phases, but only one is sent. This sequence is then
modulated on the I and Q outputs. The initial phase
reference for the data portion of the packet is the phase of
the last bit of the header. At 11Mbps, one byte is used as
above where 6 bits are used to select one of 64 spread
sequences for a symbol and the other 2 are used to QPSK
modulate that symbol. Thus, the total possible number of
combinations of sequence and carrier phases is 256. Of
these only one is sent.
Bit rates for the ISL3873 are defined in Table 6. This table
provides information on bit rates, data rates and symbol
rates for an MCLK of 44MHz clock. Figure 13 shows the
modulation schemes for the different bits rates. The
modulator is completely independent from the demodulator,
allowing the PRISM baseband processor to be used in full
duplex operation.
MODULATION
DQPSK
DBPSK
DATA
CCK
CCK
A/D SAMPLE CLOCK
(MHz)
19
HFA3683
22
22
22
22
TABLE 6. BIT RATE TABLE EXAMPLES FOR MCLK = 44MHz
HFA3783
TX SETUP CR 5
BITS 1, 0
FIGURE 12. AGC CIRCUIT
00
01
10
11
RX_RF_AGC
RX_IF_DET
RX_IF_AGC
ISL3873
RX_Q
RX_I
Header/Packet Description
The ISL3873 is designed to handle packetized Direct
Sequence Spread Spectrum (DSSS) data transmissions. The
ISL3873 generates its own preamble and header information.
It uses two packet preamble and header configurations. The
first is backwards compatible with the existing IEEE 802.11-
1997 1 and 2Mbps modes and the second is the optional
shortened mode which maximizes throughput at the expense
of compatibility with legacy equipment.
In the long preamble mode, the device uses a
synchronization preamble of 128 symbols along with a
header that includes four fields. The preamble is all 1’s
(before entering the scrambler) plus a Start Frame Delimiter
(SFD). The actual transmitted pattern of the preamble is
randomized by the scrambler. The preamble is always
transmitted as a DBPSK waveform (1Mbps). The duration of
the long preamble and header is 192 s.
In the short preamble mode, the modem uses a
synchronization field of 56 zero symbols along with an SFD
transmitted at 1Mbps. The short header is transmitted at
2Mbps. The synchronization preamble is all 0’s to distinguish
it from the long header mode and the short preamble SFD is
the time reverse of the long preamble SFD. The duration of
the short preamble and header is 96 s.
Start Frame Delimiter (SFD) Field (16 Bits)
This field is used to establish the link frame timing. The
ISL3873 will not declare a valid data packet, even if it PN
acquires, unless it detects the SFD. The ISL3873 receiver
auto-detects if the packet is long or short preamble and sets
SFD time-out. The timer starts counting after initialization of
the de-scrambler is complete.
RX SIGNAL CR 63
THRESH.
DETECT
ISL3873
BITS 7, 6
Q ADC
I ADC
DAC
IF
00
01
10
11
1
1
7
6
6
DEMOD
AGC
CTL
I/O
DATA RATE
(Mbps)
5.5
11
1
2
DATA I/O
SYMBOL RATE
(MSPS)
1.375
1.375
1
1