cs4226 Cirrus Logic, Inc., cs4226 Datasheet - Page 24

• Manufacturer Part Number: cs4226
• Description: Surround Sound Codec
• Manufacturer: Cirrus Logic, Inc.

3 REGISTER DESCRIPTION
3.1
MAP4-MAP0
INCR
This register defaults to 01h.
3.2
This byte is reserved for internal use and must be set to 00h for normal operation.
This register defaults to 00h.
3.3
CS2-CS0
CI1-CI0
CO1-CO0
This register defaults to 01h.
24
INCR
B7
B7
0
Memory Address Pointer (MAP)
Reserved Byte (00h)
Clock Mode Byte (01h)
NOTE: If the sample rate on an input pin changes while using the PLL with RX1, RX2, RX3 or RX4,
the PLL will not resynchronize to the new sample rate. You must either change input pins or change
the Clock Mode Byte to something else and then change it back to the correct value. This will cause
the PLL to resync.
CO1
B6
B6
Register Pointer
Auto Increment Control Bit
Sets the source of the master clock.
Determines frequency of XTI when PLL is disabled (not used if CS ≠ 0)
Sets CLKOUT frequency
0 - No auto increment
1 - Auto increment on
0 - Crystal Oscillator or XTI at high frequency (PLL disabled)
1 - PLL driven by LRCKAUX at 1 Fs
2 - PLL driven by LRCK at 1 Fs
3 - PLL driven by XTI at 1 Fs
4 - PLL driven by RX1 data. This changes AUX port to S/PDIF port.
5 - PLL driven by RX2 data. This changes AUX port to S/PDIF port.
6 - PLL driven by RX3 data. This changes AUX port to S/PDIF port.
7 - PLL driven by RX4 data. This changes AUX port to S/PDIF port.
0 - 256 Fs
1 - 384 Fs
2 - 512 Fs
3 - not used
0 - 256 Fs
1 - 384 Fs
2 - 512 Fs
3 - 1 Fs
0
CO0
B5
B5
0
MAP4
CI1
B4
B4
MAP3
CI0
B3
B3
MAP2
CS2
B2
B2
MAP1
CS1
B1
B1
CS4226
MAP0
DS188F4
CS0
B0
B0