cs4226 Cirrus Logic, Inc., cs4226 Datasheet - Page 25

• Manufacturer Part Number: cs4226
• Description: Surround Sound Codec
• Manufacturer: Cirrus Logic, Inc.

3.4
RS
CAL
LC
The following bits are read only:
AUTO
DU
CLKE
CALP
This register defaults to 01h
3.5
MUT6-MUT1
MUTC
ZCD
This register defaults to 3Fh.
DS188F4
CALP
ZCD
B7
B7
Converter Control Byte (02h)
DAC Control Byte (03h)
NOTE: The AC3 and MPEG detection for the AUTO bit does not look at the channel status bits. This
bit is determined by looking for the AC3/MPEG header in the data stream. See the “AC3/MPEG Auto
Detection” section earlier in the data sheet for more details.
MUTC
CLKE
B6
B6
Chip reset (Do not clear this bit until all registers have been configured as desired)
Calibration control bit
Loop Current
AC3 and MPEG Automatic Detection
Shows selected De-Emphasis setting used by DAC's
Clocking system status
Calibration status
Mute control bits
Controls mute on consecutive zeros function
Zero crossing disable
0 - No Reset
1 - Reset
0 - Normal operation
1 - Rising edge initiates calibration
0 - Normal Mode, 25 µA PLL loop current (See Figure 1 for filter component values)
1 - High Current Mode, 300 µA PLL loop current (See Figure 1 for filter component values)
0 - No AC3/MPEG Detected
1 - AC3/MPEG detected on RX/AUX
0 - Normal Flat DAC frequency response
1 - De-Emphasis selected
0 - No errors
1 - PLL is not locked, crystal is not oscillating, or requesting clock change in progress
1 - Calibration in progress
0 - Calibration done. This register defaults to 01h
0 - Normal output level
1 - Selected DAC output muted
0 - 512 consecutive zeros will mute DAC
1 - DAC output will not mute on zeros
0 - DAC mutes and volume control changes occur on zero-crossings.
1 - DAC mutes and volume control changes occur immediately.
MUT6
DU
B5
B5
AUTO
MUT5
B4
B4
MUT4
B3
LC
B3
MUT3
B2
B2
0
MUT2
CAL
B1
B1
CS4226
MUT1
RS
B0
B0
25