cs4226 Cirrus Logic, Inc., cs4226 Datasheet - Page 28

• Manufacturer Part Number: cs4226
• Description: Surround Sound Codec
• Manufacturer: Cirrus Logic, Inc.

3.11 DSP Port Mode Byte (0Eh)
DDF2-DDF0
DSCK
DMS1-DMS0
DCK1-DCK0 *
This register defaults to 00h.
* DCK1-DCK0 are ignored in formats 5 and 6.
28
DCK1
B7
DCK0
B6
Set number of bit clocks per Fs period
Data format
Set the polarity of clocking data
Sets the mode of the port
0 - Right justified, 20-bit
1 - Right justified, 18-bit
2 - Right justified, 16-bit
3 - Left justified, 20-bit in / 24-bit out
4 - I
5 - One Data Line Mode (Figure 6)
6 - One Data Line (Master Mode only, Figure 6)
7 - Not used
0 - Data clocked in on rising edge of SCLK, out on falling edge of SCLK
1 - Data clocked in on falling edge of SCLK, out on rising edge of SCLK
0 - Slave
1 - Master Burst - SCLKs are gated 128 fs clocks
2 - Master Non-Burst - SCLKs are evenly distributed (No 48 fs SCLK)
3 - not used - default to Slave
0 - 128
1 - 48 - Master Burst or Slave mode only
2 - 32 - All formats will default to 16 bits
3 - 64
2
S compatible, 20-bit in / 24-bit out
DMS1
B5
DMS0
B4
DSCK
B3
DDF2
B2
DDF1
B1
CS4226
DDF0
DS188F4
B0