cs89712 Cirrus Logic, Inc., cs89712 Datasheet - Page 103

• Manufacturer Part Number: cs89712
• Description: High-performance, Low-power System-on-chip With 10base-t Ethernet Controller
• Manufacturer: Cirrus Logic, Inc.

3.11.4 FBADDR LCD Frame Buffer Start Address (address 0x8000.1000)
This register contains the start address for the LCD Frame Buffer. It is assumed that the frame buffer starts at loca-
tion 0x0000000 within each chip select memory region. Therefore, the value stored within the FBADDR register is
only the value of the chip select where the frame buffer is located. On reset, this will be set to 0xC. The register is 4
bits wide (bits [3:0]). This register must only be reprogrammed when the LCD is disabled (i.e., setting the LCDEN
bit within SYSCON2 low), or during the period after exit from Snooze State before the LCDSNZE bit has been reset
(i.e. while data is still being displayed from the on-chip SRAM in 1 bit per pixel mode).
3.12 SSI Register
3.12.1 SYNCIO Synchronous Serial ADC Interface Data Register (address 0x8000.0500)
SYNCIO is a 32-bit read / write register. The data written to the SYNCIO register configures the master only SSI. In
default mode, the least significant byte is serialized and transmitted out of the synchronous serial interface1 (i.e.,
SSI1) to configure an external ADC, MSB first. In extended mode, a variable number of bits are sent from SYN-
CIO[16:31] as determined by the ADC Configuration Length. The transfer clock will automatically be started at the
programmed frequency and a synchronization pulse will be issued. The ADCIN pin is sampled on every positive go-
ing clock edge (or the falling clock edge, if ADCCKNSEN in SYSCON3 is set) and the result is shifted in to the SYN-
CIO read register.
During data transfer, the SSIBUSY bit is set high; at the end of a transfer the SSEOTI interrupt will be asserted. To
clear the interrupt the SYNCIO register must be read. The data read from the SYNCIO register is the last sixteen
bits shifted out of the ADC.
The length of the data frame can be programmed by writing to the SYNCIO register. This allows many different ADCs
to be accommodated. The device is SPI- / Microwire-compatible (transfers are in multiples of 8 bits). However, to be
compatible with some non-SPI / Microwire devices, the data written to the ADC device can be anything between 8
to 16 bits. This is user-definable per the ADC Configuration Extension section of the SYNCIO register.
DS502PP2
In the default mode, the bits in SYNCIO have the following meaning:
Whereas in extended mode, the following applies:
Note:
0:7 or 0:6
Reserved
Reserved
Bit
31:15
15
The frame length in extended mode is 6 bits wide to allow up to 16 write bits, 1 null bit and 16 read bits (=
33 cycles).
ADC Configuration Byte: When the ADCCON control bit in the SYSCON3 register = 0, this is
the 8-bit configuration data to be sent to the ADC. When the ADCCON control bit in the
SYSCON3 register = 1, this field determines the length of the ADC configuration data held in the
ADC Configuration Extension field for sending to the ADC.
TXFRMEN
TXFRMEN
14
14
SMCKEN
SMCKEN
13
13
Table 57. SYNCIO
Description
Frame length
Frame length
12:8
12:7
ADC Configuration Length
ADC Configuration Byte
7:0
6:0
CS89712
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