cs89712 Cirrus Logic, Inc., cs89712 Datasheet - Page 35

• Manufacturer Part Number: cs89712
• Description: High-performance, Low-power System-on-chip With 10base-t Ethernet Controller
• Manufacturer: Cirrus Logic, Inc.

frame synchronization. Each transition of LRCK
delineates the left and right halves of an audio sam-
ple. When LRCK transitions from high-to-low the
next 16 bits make up the right side of a sample.
When LRCK transitions from low-to-high the next
16 bits make up the left side of a sample.
2.17.2.3 DAI Signals
MCLK is used as an input to the CS89712 for gen-
erating the DAI timing. This signal is also usually
used as an input to a DAC/ADC as an oversampled
clock. This signal is fixed at 256 times the audio
sample frequency.
DS502PP2
SDATA
SDATA
SDATAI
LRCK
SCLK
O
(73.728MHz)
(11.2896)
EXTCLK
PLL
MSB
MSB
Figure 8. CS89712 - Digital Audio Interface Timing – MSB / Left Justified format
-1 -2 -3 -4 -5
-1 -2 -3 -4 -5
-1 -2 -3 -4 -5
/
2
(AUDCLKSRC)
+5 +4
+5 +4
Left Channel
+5 +4
MUX
+3 +2 +1
+3 +2 +1
+3 +2 +1
Figure 7. Digital Audio Clock Generation
Programmable Divide
LSB
LSB
(AUDIV)
128 SCLKs
256Fs
128(fs)
The SCLKbit clock is used as the bit clock input
into the DAC/ADC. This signal is fixed at 128 or
64 times the audio sample frequency.
LRCK is used as a frame synchronization input to
the DAC/ADC. This signal is fixed at the audio
sample frequency. This signal is clocked out on the
negative going edge of SCLK.
SDOUT is used for sending playback data to a
DAC. This signal is clocked out on the negative go-
ing edge of the SCLK output.
SDIN is used for receiving record data from an
ADC. This signal is latched by the CS89712 on the
positive going edge of SCLK.
/32
DAI
MSB
MSB
-1 -2 -3 -4
-1 -2 -3 -4
-1 -2 -3 -4
Audio Bit Clock 128/64(fs) SCLK
fixed at 4
counter
7-bit
BUZZ
+5 +4
+5 +4
+5 +4
Right Channel
MCLK
Frequency
Sample
+3 +2 +1
+3 +2 +1
+3 +2 +1
Audio
(fs)
LSB
LSB
BUZZ-PIN
LRCLK(Fs)
Control
Audio
FIFO
Data
CS89712
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