ltc2203 Linear Technology Corporation, ltc2203 Datasheet - Page 16

• Manufacturer Part Number: ltc2203
• Description: 16-bit, 25msps Adc
• Manufacturer: Linear Technology Corporation

PI FU CTIO S
LTC2203/LTC2202
SENSE (Pin 1): Reference Mode Select and External Refer-
ence Input. Tie SENSE to V
the internal 2.5V bandgap reference. An external reference
of 2.5V or 1.25V may be used; both reference values will
set a full scale ADC range of 2.5V (PGA = 0).
V
mon mode. Must be bypassed to ground with a minimum
of 2.2µF. Ceramic chip capacitors are recommended.
V
Bypass to GND with 0.1µF ceramic chip capacitors.
GND (Pins 5, 8, 9, 11, 15, 48, 49): ADC Power
Ground.
A
A
CLK (Pin 10): Clock Input. The hold phase of the sample-
and-hold circuit begins on the falling edge. The output
data may be latched on the rising edge of CLK.
SHDN (Pin 16): Power Shutdown Pin. SHDN = low results
in normal operation. SHDN = high results in powered
down analog circuitry and the digital outputs are placed
in a high impedance state.
DITH (Pin 17): Internal Dither Enable Pin. DITH = low
disables internal dither. DITH = high enables internal
dither. Refer to Internal Dither section of this data sheet
for details on dither operation.
D0-D15 (Pins 18-22, 26-28, 32-35 and 39-42): Digital
Outputs. D15 is the MSB.
OGND (Pins 23, 31 and 38): Output Driver Ground.
OV
16
CM
DD
IN
IN
U
DD
+
–
(Pin 2): 1.25V Output. Optimum voltage for input com-
(Pins 3, 4, 12, 13, 14): 3.3V Analog Supply Pin.
(Pin 6): Positive Differential Analog Input.
(Pin 7): Negative Differential Analog Input.
(Pins 24, 25, 36, 37): Positive Supply for the Output
U
U
DD
with 1k Ω or less to select
Drivers. Bypass to ground with 0.1µF capacitor.
CLKOUT
at the sample rate. Latch the data on the falling edge of
CLKOUT
CLKOUT
will toggle at the sample rate. Latch the data on the rising
edge of CLKOUT
OF (Pin 43): Over/Under Flow Digital Output. OF is high
when an over or under fl ow has occurred.
⎯ O ⎯ E (Pin 44): Output Enable Pin. Low enables the digital
output drivers. High puts digital outputs in Hi-Z state.
MODE (Pin 45): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and disables the clock duty
cycle stabilizer. Connecting MODE to 1/3V
binary output format and enables the clock duty cycle sta-
bilizer. Connecting MODE to 2/3V
output format and enables the clock duty cycle stabilizer.
Connecting MODE to V
format and disables the clock duty cycle stabilizer.
RAND (Pin 46): Digital Output Randomization Selection Pin.
RAND low results in normal operation. RAND high selects
D1-D15 to be EXCLUSIVE-ORed with D0 (the LSB). The
output can be decoded by again applying an XOR operation
between the LSB and all other bits. The mode of operation
reduces the effects of digital output interference.
PGA (Pin 47): Programmable Gain Amplifi er Control Pin. Low
selects a front-end gain of 1, input range of 2.5V
selects a front-end gain of 1.5, input range of 1.667V
GND (Exposed Pad, Pin 49): ADC Power Ground. The ex-
posed pad on the bottom of the package must be soldered
to ground.
–
–
+
.
(Pin 29): Data Valid Output. CLKOUT
(Pin 30): Inverted Data Valid Output. CLKOUT
+
.
DD
selects 2’s complement output
DD
selects 2’s complement
DD
selects offset
–
will toggle
P-P
. High
P-P
22032fb
.
+