ltc2203 Linear Technology Corporation, ltc2203 Datasheet - Page 19

• Manufacturer Part Number: ltc2203
• Description: 16-bit, 25msps Adc
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
CONVERTER OPERATION
The LTC2203/LTC2202 are CMOS pipelined multistep con-
verters with a front-end PGA. As shown in Figure 1, the con-
verter has fi ve pipelined ADC stages; a sampled analog input
will result in a digitized value seven cycles later (see the
Timing Diagram section). The analog input is differential for
improved common mode noise immunity and to maximize
the input range. Additionally, the differential input drive
will reduce even order harmonics of the sample-and-hold
circuit.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage amplifi er. In
operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplifi ed and
output by the residue amplifi er. Successive stages oper-
ate out of phase so that when odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
The phase of operation is determined by the state of the
CLK input pin.
When CLK is high, the analog input is sampled differen-
tially directly onto the input sample-and-hold capacitors,
inside the “input S/H” shown in the block diagram. At the
instant that CLK transitions from high to low, the voltage
on the sample capacitors is held. While CLK is low, the
held input voltage is buffered by the S/H amplifi er which
drives the fi rst pipelined ADC stage. The fi rst stage acquires
the output of the S/H amplifi er during the low phase of
CLK. When CLK goes back high, the fi rst stage produces
its residue which is acquired by the second stage. At the
same time, the input S/H goes back to acquiring the analog
input. When CLK goes low, the second stage produces its
residue which is acquired by the third stage. An identi-
cal process is repeated for the third and fourth stages,
resulting in a fourth stage residue that is sent to the fi fth
stage for fi nal evaluation.
Each ADC stage following the fi rst has additional range to
accommodate fl ash and amplifi er offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.
U
U
W
U
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2203/
LTC2202 CMOS differential sample and hold. The differ-
ential analog inputs are sampled directly onto sampling
capacitors (C
capacitors shown attached to each input (C
the summation of all other capacitance associated with
each input.
During the sample phase when CLK is high, the NMOS
transistors connect the analog inputs to the sampling
capacitors and they charge to, and track the differential
input voltage. When CLK transitions from high to low, the
sampled input voltage is held on the sampling capacitors.
During the hold phase when CLK is high, the sampling
capacitors are disconnected from the input and the held
voltage is passed to the ADC core for processing. As CLK
transitions from low to high, the inputs are reconnected to
the sampling capacitors to acquire a new sample. Since
the sampling capacitors still hold the previous sample,
a charging glitch proportional to the change in voltage
between samples will be seen at this time at the input of
the converter. If the change between the last sample and
A
A
CLK
IN
IN
+
–
LTC220
3/02
V
V
Figure 2. Equivalent Input Circuit
SAMPLE
DD
DD
LTC2203/LTC2202
) through NMOS transitors. The
C
1.4pF
C
1.4pF
PARASITIC
PARASITIC
PARASITIC
C
C
SAMPLE
SAMPLE
9.1pF
9.1pF
19
22032 F02
) are
22032fb