ltc2203 Linear Technology Corporation, ltc2203 Datasheet - Page 23

• Manufacturer Part Number: ltc2203
• Description: 16-bit, 25msps Adc
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
DIGITAL OUTPUTS
Digital Output Buffers
Figure 9 shows an equivalent circuit for a single output
buffer in CMOS Mode. Each buffer is powered by OV
and OGND, isolated from the ADC power and ground. The
additional N-channel transistor in the output driver allows
operation down to low voltages. The internal resistor in
series with the output makes the output appear as 50Ω
to external circuitry and eliminates the need for external
damping resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2203/LTC2202 should drive a
minimum capacitive load to avoid possible interaction
between the digital outputs and sensitive input circuitry.
The output should be buffered with a device such as a
ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF. A resistor in
series with the output may be used but is not required
since the ADC has a series resistor of 43Ω on chip.
Lower OV
from the digital outputs.
LATCH
FROM
DATA
Figure 9. Equivalent Circuit for a Digital Output Buffer
PREDRIVER
LOGIC
DD
V
DD
voltages will also help reduce interference
U
U
V
DD
W
OV
LTC2203/02
DD
43Ω
22032 F10
U
OV
OGND
DD
TYPICAL
DATA
OUTPUT
0.5V
TO 3.6V
0.1μF
DD
Data Format
The LTC2203/LTC2202 parallel digital output can be
selected for offset binary or 2’s complement format. The
format is selected with the MODE pin. This pin has a four
level logic input, centered at 0, 1/3V
An external resistor divider can be user to set the 1/3V
and 2/3V
for the MODE pin.
Table 1. MODE Pin Function
Overfl ow Bit
An overfl ow output bit (OF) indicates when the converter
is over-ranged or under-ranged. A logic high on the OF
pin indicates an overfl ow or underfl ow.
Output Clock
The ADC has a delayed version of the CLK input available
as a digital output. Both a noninverted version, CLKOUT
and an inverted version CLKOUT
CLKOUT
verter data to the digital system. This is necesary when
using a sinusoidal clock. Data can be latched on the ris-
ing edge of CLKOUT+ or the falling edge of CLKOUT–.
CLKOUT+ falls and CLKOUT– rises as the data outputs
are updated.
0(GND)
1/3V
2/3V
MODE
V
DD
+
DD
DD
DD
/CLKOUT
logic levels. Table 1 shows the logic states
–
LTC2203/LTC2202
can be used to synchronize the con-
2’s Complement
2’s Complement
Output Format
Offset Binary
Offset Binary
–
DD
are provided. The
, 2/3V
Cycle Stabilizer
Clock Duty
DD
Off
On
On
Off
and V
23
22032fb
DD
DD
+
.