mcs1000 MosChip, mcs1000 Datasheet - Page 24

• Manufacturer Part Number: mcs1000
• Description: Security Processor
• Manufacturer: MosChip

MCS1000
Security Processor
Serial EEPROM Interface
The Serial EEPROM interface can be used to interface to any SPI device. Primarily it is used to interface to a
Serial EEPROM that is used to store the MAC addresses of the three (3) Ethernet controllers along with PCI
information. The serial device can also store additional user defined information.
PCI Interface
The MCS1000 contains a device only 32-bit 33MHz interface conforming to the PCI Local Bus Specification 2.2.
The MCS1000 does not contain an internal PCI arbiter, but it can master the PCI bus as a device.
Memory Controller
There is a Memory Management Unit (MMU) and a Memory Controller (MC). The MMU and the MC sit on
opposite sides of the AHB to VCI bridge. The MMU sits between the ARM9 and the AHB BIU and the MC sits
on the VCI bus and interfaces with external memory (SDRAM and Flash) and the Local-bus. For information
on the MMU see the CPU Subsystem section of this document.
SDRAM Interface
The SDRAM interface is a 100MHz 32-bit interface. The maximum SDRAM capacity is 64 Megabytes.
Flash Interface
The Flash interface can be 8-, 16-, or 32-bits wide. There are 26 address lines that yield a maximum storage of
64Megabytes with an 8-bit bus, 128Megabytes with a 16-bit bus, and 256Megabytes with a 32-bit bus width.
Local Bus Interface
The local bus interface can be 8-, 16-, or 32-bits wide. The local bus interface waveforms are programmable
enabling access to different target devices. The bus transaction can be extended by asserting the ready input
signal. The polarity of this control input is programmable. The GPIO pins can be programmed to generate
interrupts.
Serial Port
The Serial port uses a standard 16550-compatible UART and it is fully pinned with TX, RX, RTS, CTS, DSR,
DTR, DCD, and RI. This port is uses standard digital levels. A common RS-232 driver is required in order
to achieve standard RS-232 levels. The registers in the UART are compatible with the 16550 and code that
interfaces with a standard 16550 should interface with the UART in the MCS1000. BAUD rates can range from
1200 BAUD to 115.2K BAUD.
General Purpose I/O
There are 16 GPIO pins. Each GPIO can be configured independently of all other GPIOs. The GPIOs allow
data input and IRQ generation.
Clock Circuit
All clocks throughout the MCS1000 are generated via a single external 25 MHz crystal.
Bootstraps
There are certain attributes of the MCS1000 that need to be set-up before reset becomes inactive. These
configuration settings are controlled via a bootstrap register. The bootstrap register is loaded with values based
on the logic levels of the ADC address bus pins immediately after reset is inactivated.
The bootstraps control four main aspects of the MCS1000: Debug mode, Processor speed, Internal ROM
disable and User defined
Page 24
Rev.
1.1