ltc3831egn-trpbf Linear Technology Corporation, ltc3831egn-trpbf Datasheet - Page 12

• Manufacturer Part Number: ltc3831egn-trpbf
• Description: High Power Synchronous Switching Regulator Controller For Ddr Memory Termination
• Manufacturer: Linear Technology Corporation

than 7V, a 12V zener diode should be included from PV
to PGND to prevent transients from damaging the circuitry
at PV
For applications with a lower V
pump circuit shown in Figure 7 can be used to provide
2V
MOSFETs respectively. This circuit provides 3V
PV
is the forward voltage of the Schottky diode. The circuit
requires the use of Schottky diodes to minimize forward
drop across the diodes at start-up. The tripling charge
pump circuit can rectify any ringing at the drain of Q2 and
provide more than 3V
be included from PV
damaging the circuitry at PV
The charge pump capacitors for PV
BG pin goes high and the switch node is pulled low by
Q2. The BG on time becomes narrow when the LTC3831
operates at maximum duty cycle (95% typical) which
can occur if the input supply rises more slowly than the
soft-start capacitor or the input voltage droops during
load transients. If the BG on time gets so narrow that the
switch node fails to pull completely to ground, the charge
pump voltage may collapse or fail to start causing excessive
dissipation in external MOSFET Q1. This is most likely with
low V
with large external MOSFETs that slow the BG and switch
node slew rates.
The LTC3831 overcomes this problem by sensing the
PV
above V
70% by clamping the COMP pin at 1.8V (Q
Diagram). This increases the BG on time and allows the
charge pump capacitors to be refreshed.
For applications using an external supply to power PV
this supply must also be higher than V
to ensure normal operation.
APPLICATIONS INFORMATION
LTC3831
12
IN
CC1
CC1
and 3V
CC1
CC
voltage when TG is high. If PV
while Q1 is ON and 2V
voltages and high switching frequencies, coupled
CC
or the gate of Q1.
, the maximum TG duty cycle is reduced to
IN
gate drive for the external top and bottom
CC1
IN
to PGND to prevent transients from
at PV
CC1
CC1
IN
IN
; a 12V zener diode should
– 2V
or the gate of Q1.
supply, a tripling charge
CC1
CC1
F
to PV
CC
refresh when the
is less than 2.5V
by at least 2.5V
C
CC2
in the Block
IN
where V
– 3V
CC1
F
CC1
to
F
,
Connecting the Ratiometric Reference Input
The LTC3831 derives its ratiometric reference, V
ing an internal resistor divider. The top and bottom of
the resistor divider is connected to the R
respectively. This permits the output voltage to track at
a ratio of the differential voltage at R
The LTC3831 can operate with a minimum V
and maximum V
to GND, this gives a V
– 3.5V). If V
increase the V
In a typical DDR memory termination application as shown
in Figure 1, R
of the interface, and R
connected to the FB pin, so V
If a ratio greater than 0.5 is desired, it can be achieved
using an external resistor divider connected to V
FB pin. Figure 8 shows an application that generates a
V
TT
of 0.6 • V
10μF
D
12V
1N5242
Z
LTC3831
PV
1N5817
R
CC2
+
DDQ
+
CC
Figure 7. Tripling Charge Pump
is higher than the permitted input voltage,
is connected to V
FB
.
voltage to raise the input range.
PV
1N5817
of (V
CC1
TG
BG
–
R
+
to GND. The output voltage V
CC
input range of 2.2V to (2 • V
0.1μF
– 1.75V). With R
TT
= 0.5 • V
1N5817
0.1μF
DDQ
V
, the supply voltage
+
IN
Q1
Q2
and R
DDQ
L
+
O
and R
.
–
–
.
FB
connected
+
of 1.1V
REF
3831 F07
TT
–
C
OUT
, us-
pins
TT
3831fa
V
and
OUT
CC
is