ltc3831egn-trpbf Linear Technology Corporation, ltc3831egn-trpbf Datasheet - Page 8

• Manufacturer Part Number: ltc3831egn-trpbf
• Description: High Power Synchronous Switching Regulator Controller For Ddr Memory Termination
• Manufacturer: Linear Technology Corporation

TEST CIRCUITS
LTC3831
OVERVIEW
The LTC3831 is a voltage mode feedback, synchronous
switching regulator controller (see Block Diagram) de-
signed for use in high to medium power, DDR memory
termination. It includes an onboard PWM generator, a
ratiometric reference, two high power MOSFET gate
drivers and all necessary feedback and control circuitry
to form a complete switching regulator circuit. The PWM
loop nominally runs at 200kHz.
The LTC3831 is designed to generate an output volt-
age that tracks at 1/2 of the external voltage connected
between the R
to generate the termination voltage, V
the SSTL_2 where V
voltage, V
standard for V
improve noise immunity. Using the LTC3831 to supply the
interface termination voltage allows large current sourc-
ing and sinking through the termination resistors during
bus transitions.
The LTC3831 includes a current limit sensing circuit that
uses the topside external N-channel power MOSFET as
a current sensing element, eliminating the need for an
external sense resistor. Also included is an internal soft-
start feature that requires only a single external capacitor
to operate. In addition, the part features an adjustable
oscillator which can free run or synchronize to an external
signal with frequencies from 100kHz to 500kHz, allowing
added fl exibility in external component selection.
APPLICATIONS INFORMATION
8
DDQ
. It is a requirement in the SSTL_2 interface
TT
+
and R
to track the interface supply voltage to
TT
–
is a ratio of the interface supply
pins. The LTC3831 can be used
V
COMP
2.5V
V
NC
NC
FB
TT
, for interface like
SS
FREQSET
FB
COMP
R
+
V
SHDN
SHDN
R
–
V
V
CC
CC
I
MAX
LTC3831
PV
CC2
Figure 2
GND
PV
PV
CC1
CC
THEORY OF OPERATION
Primary Feedback Loop
The LTC3831 senses the output voltage of the circuit
through the FB pin and feeds this voltage back to the
internal transconductance error amplifi er, ERR. The er-
ror amplifi er compares the output voltage to the internal
ratiometric reference, V
the PWM comparator. V
voltage difference between the R
internal resistor divider.
This error signal is compared with a fi xed frequency
ramp waveform, from the internal oscillator, to generate
a pulse width modulated signal. This PWM signal drives
the external MOSFETs through the TG and BG pins. The
resulting chopped waveform is fi ltered by L
which closes the loop. Loop compensation is achieved
with an external compensation network at the COMP pin,
the output node of the error amplifi er.
MIN, MAX Feedback Loops
Two additional comparators in the feedback loop provide
high speed output voltage correction in situations where
the error amplifi er may not respond quickly enough. MIN
compares the feedback signal to a voltage 3% below V
If the signal is below the comparator threshold, the MIN
comparator overrides the error amplifi er and forces the
loop to maximum duty cycle, >91%. Similarly, the MAX
comparator forces the output to 0% duty cycle if the feed-
PGND
I
FB
3831 F02
BG
TG
+
10μF
6800pF
6800pF
TG RISE/FALL
BG RISE/FALL
0.1μF
REF
REF
, and outputs an error signal to
is set to 0.5 multiplied by the
+
and R
–
pins, using an
O
and C
3831fa
OUT
REF
.