ltc3831egn-trpbf Linear Technology Corporation, ltc3831egn-trpbf Datasheet - Page 18

• Manufacturer Part Number: ltc3831egn-trpbf
• Description: High Power Synchronous Switching Regulator Controller For Ddr Memory Termination
• Manufacturer: Linear Technology Corporation

APPLICATIONS INFORMATION
LTC3831
LAYOUT CONSIDERATIONS
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3831. These items are also illustrated graphically
in the layout diagram of Figure 10. The thicker lines show
the high current paths. Note that at 5A current levels or
above, current density in the PC board itself is a serious
concern. Traces carrying high current should be as wide as
possible. For example, a PCB fabricated with 2oz copper
requires a minimum trace width of 0.15” to carry 5A .
1. In general, layout should begin with the location of
the power devices. Be sure to orient the power circuitry
so that a clean power fl ow path is achieved. Conductor
widths should be maximized and lengths minimized. After
you are satisfi ed with the power path, the control circuitry
should be laid out. It is much easier to fi nd routes for the
relatively small traces in the control circuits than it is to
fi nd circuitous routes for high current paths.
2. The GND and PGND pins should be shorted directly
at the LTC3831 . This helps to minimize internal ground
disturbances in the LTC3831 and prevents differences in
ground potential from disrupting internal circuit operation.
This connection should then tie into the ground plane
at a single point, preferably at a fairly quiet point in the
circuit such as close to the output capacitors . This is not
always practical, however, due to physical constraints.
Another reasonably good point to make this connection is
between the output capacitors and the source connection
of the bottom MOSFET Q2. Do not tie this single point
18
ground in the trace run between the Q2 source and the
input capacitor ground, as this area of the ground plane
will be very noisy.
3. The small-signal resistors and capacitors for frequency
compensation and soft-start should be located very close
to their respective pins and the ground ends connected
to the signal ground pin through a separate trace. Do not
connect these parts to the ground plane!
4. The V
be as close to the LTC3831 as possible. The 4.7μF and
1μF bypass capacitors shown at V
help provide optimum regulation performance.
5. The (+) plate of C
possible to the drain of the upper MOSFET, Q1. An ad-
ditional 1μF ceramic capacitor between V
ground is recommended.
6. The V
node. Care should be taken to isolate V
capacitive coupling to the inductor switching signal.
7. In a typical SSTL application, if the R
nected to V
the switching regulator, do not connect R
current flow path; it should be connected to the SSTL
interface supply output. R
interface supply GND.
8. Kelvin sense I
CC
FB
, PV
pin is very sensitive to pickup from the switching
DDQ
CC1
, which is also the main supply voltage for
MAX
and PV
and I
IN
should be connected as close as
CC2
FB
–
decoupling capacitors should
at Q1’s drain and source pins.
should be connected to the
CC
, PV
CC1
+
FB
pin is to be con-
+
along the high
from possible
and PV
IN
and power
CC2
3831fa
will