ltc4221 Linear Technology Corporation, ltc4221 Datasheet - Page 13

• Manufacturer Part Number: ltc4221
• Description: Dual Hot Swap Controller/power Sequencer With Dual Speed, Dual Level Fault Protection
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
Undervoltage Lockout
An internal undervoltage lockout (UVLO) occurs if either
V
is kept in lockout mode in which the internal charge pumps
are off, the GATE pins, TIMER are held low by internal
N-channel MOSFET pull-downs and the FAULT latch reset,
cutting off both channels. V
threshold of 2.5V with 110mV hysteresis. V
to-high UVLO threshold of 0.8V with 25mV hysteresis.
Both UVLOs have glitch filters that filter out dips that are
less than 30μs, allowing for bus supply transients. An
additional requirement for normal operation is V
V
ON Pin Functions
The ON1 pin serves as a global reset for the LTC4221. It
has an internal reset comparator with a high-to-low thresh-
old of 0.4V, a 25mV hysteresis and a high-to-low glitch
filter of 15μs. Pulling ON1 below this threshold will put the
LTC4221 into a reset state in which the TIMER is pulled low
by an internal N-channel MOSFET pull-down, the GATE
pins are pulled low by separate internal 100μA pull-downs
and the FAULT latch resets. A low-to-high transition on the
ON1 pin past the reset threshold releases the reset on the
FAULT latch and both channels go into an off state.
V
V
CC1
CC2
CC
CC2
supply is too low for normal operation. The LTC4221
.
CONNECTOR
BACKPLANE
Z1 = SMAJ10
* ADDITIONAL DETAILS
(FEMALE)
OMITTED FOR CLARITY
CONNECTOR
PCB EDGE
(MALE)
U
LONG
LONG
SHORT
LONG
U
10k
R2
CC1
(2a) Circuit
Z1
R1
10k
has a low-to-high UVLO
16
10
1
W
ON1
ON2
GND
LTC4221*
R
10Ω
TIMER
X1
C
100nF
X1
SENSE1
GATE1
9
V
FB1
CC1
C
1μF
TIMER
Figure 2. Simultaneous Power On/Off
CC2
R
0.004Ω
U
has a low-
SENSE1
CC1
IRF7413
Q1
≥
R
56k
R
15k
F1
F2
+
In addition to its global reset function, ON1 also serves as
an on/off switch for channel 1. ON2 performs the same
role for channel 2. Both pins have an off comparator with
a high-to-low threshold of 0.821V and 30mV hysteresis.
With these, ON1 and ON2 can be used to force a simulta-
neous or sequential power-up/power-down of the two
channels. A simultaneous power-up and power-down is
shown in Figure 2b. Both V
UVLO at time point 1 and both channels enter reset state.
When ON1 clears its reset threshold, either ON1 or ON2
clears its off threshold, both GATEs < 0.4V and TIMER <
0.4V (time point 2), an initial timing cycle starts. At time
point 4, the initial timing cycle completes and the LTC4221
checks that FILTER is low and FAULT is high. If both
conditions are met, it then monitors the voltage of ON1 and
ON2. As long as its ON pin has cleared its off threshold,
each channel powers up regardless of the state of the other
channel. Similarly, if its ON pin goes below its off thresh-
old, each channel pulls its GATE pin down with an internal
100μA pull-down and turns off its external MOSFET re-
gardless of the state of the other channel. As the circuit in
Figure 2a has its two ON pins shorted together, a simulta-
neous power-up is programmed at time points 4 to 5 and
a simultaneous power down is programmed between time
points 7 and 8. The timing waveforms in Figure 3 show a
4221 F02a
C
LOAD1
V
3.3V
5A
V
2.5V
5A
OUT1
OUT2
TIMER
GATE n
V
V
OUT n
ON n
CC n
UVLO
RESET STATE
0.851V
1
V
CC n (UVL)
1.9μA
(2b) Timing Waveforms
2
1.234V
INITIAL
TIMING
CC
3 4
START-UP
CHANNEL
pins clear their respective
9.5μA
20μA
V
TH
5 6
NORMAL
0.821V
LTC4221
7 8
RESET
100μA
13
DISCHARGE
BY LOAD
4221 F02b
4221fa