ltc4221 Linear Technology Corporation, ltc4221 Datasheet - Page 9

• Manufacturer Part Number: ltc4221
• Description: Dual Hot Swap Controller/power Sequencer With Dual Speed, Dual Level Fault Protection
• Manufacturer: Linear Technology Corporation

PI FU CTIO S
GATE1 (Pin 4): Channel 1 Gate Drive. This pin is the high
side gate drive of an external N-channel MOSFET. When
V
source. When V
followed by a start-up cycle when an internal charge pump
provides a 9.5μA pull-up to ramp up GATE1 with inrush
current limiting. UVLO, overvoltage, overcurrent and ex-
ternally generated faults override the ON1 pin and pull
GATE1 low.
FB1 (Pin 5): V
channel 1 output voltage with an external resistive divider.
When V
V
set and both GATEs are pulled low. The FB1 pin is also used
to control the channel 1 current limit during its start-up
cycle.
PWRGD1 (Pin 6): Channel 1 Power Good Output. PWRGD1
is pulled low when V
cycle or when the chip is in UVLO. An external pull-up is
required to generate a logic high at the open-drain PWRGD1
pin.
FAULT (Pin 7): Fault Status Input/Output. FAULT is a
bidirectional pin. As an input, pulsing V
set the FAULT latch and bring the LTC4221 into the fault
state. As an output, FAULT is pulled high by an internal
3.8μA pull-up under normal operating conditions. When
an overcurrent fault is detected by a SENSE pin or a
overvoltage fault detected by an FB pin, the FAULT latch is
set and the LTC4221 goes into the fault state. The FAULT
latch is reset by a UVLO or the ON1 pin being driven below
0.4V.
FILTER (Pin 8): Overcurrent Fault Timing Filter. The
FILTER pin requires an external capacitor to ground to
adjust the response time of the two slow comparators. The
FILTER pin can be left unconnected for a default slow
comparator response time of 15μs.
ON1
FB1
U
> 0.822V, overvoltage is detected, the FAULT latch is
< 0.821V, GATE1 is held low by a 100μA current
FB1
U
< 0.617V, the PWRGD1 pin is pulled low. When
OUT1
ON1
U
FB1
> 0.851V, an initial timing cycle is
Feedback Input. FB1 monitors the
< 0.617V, during the initial timing
FAULT
< 0.816V will
TIMER (Pin 9): Analog System Timer. The TIMER pin
requires an external capacitor to ground to generate
timing delay cycles during start-up. The LTC4221’s initial
and start-up timing cycles are controlled by C
internal current sources connected to the TIMER pin.
GND (Pin 10): Ground. Connect to a ground plane for
optimum performance.
PWRGD2 (Pin 11): Channel 2 Power Good Output. Similar
functionality as PWRGD1. Controlled by FB2.
FB2 (Pin 12): V
as FB1. Monitors channel 2 output voltage, controls
PWRGD2 output and channel 2 start-up current limit.
GATE2 (Pin 13): Channel 2 Gate Drive. Similar functional-
ity as GATE1. Controls the gate drive of the channel 2
external N-channel MOSFET. ON2 controls GATE2 in the
same manner as ON1 controls GATE1. V
rides conditions at ON2 and GATE2 is held low by a 100μA
current source. UVLO, overvoltage, overcurrent and exter-
nally generated faults override conditions at ON1 and ON2,
and pull GATE2 low.
SENSE2 (Pin 14): Channel 2 Current Sense Input. Similar
functionality as SENSE1. Monitors channel 2 load current
through R
and SENSE2. To disable the current limit and circuit
breaker function for channel 2, tie SENSE2 to V
V
range from 1V to 13.5V for normal operation but it must
be ≤V
channels whenever the voltage at V
ON2 (Pin 16): Channel 2 On Input. GATE2 is pulled to
ground by a 100μA current source when V
When V
timing cycle.
CC2
(Pin 15): Channel 2 Positive Supply Input. V
CC1
ON2
. An undervoltage lockout circuit disables both
SENSE2
> 0.851V, GATE2 ramps up after an initial
OUT2
placed in the supply path between V
Feedback Input. Similar functionality
CC2
is less than 0.8V.
ON1
LTC4221
ON2
TIMER
< 0.4V over-
< 0.821V.
CC2
CC2
and the
.
4221fa
9
can
CC2