nt1gt64uh8c0fn Nanya Techology, nt1gt64uh8c0fn Datasheet - Page 5

• Manufacturer Part Number: nt1gt64uh8c0fn
• Description: Based On Ddr2-533/667/800 64mx16 1gb /128mx8 2gb Sdram C-die
• Manufacturer: Nanya Techology

NT1GT64UH8C0FN / NT2GT64U8HC0BN
1GB: 128M x 64 / 2GB: 256M x 64
PC2-4200 / PC2-5300 / PC2-6400
Unbuffered DDR2 SO-DIMM
Input/Output Functional Description
REV 1.1
02/2008
BA0, BA1, BA2
DQS0 – DQS7
A11, A12/A13
CKE0, CKE1
ODT0, ODT1
DQ0 – DQ63
DM0 – DM7
SA0 – SA1
CK0, CK1
A0 – A9
V
Symbol
A10/AP
V
,
DD
SDA
V
SCL
DDSPD
REF
–
,
,
,
V
SS
,
(SSTL)
(SSTL)
(SSTL)
(SSTL)
(SSTL)
(SSTL)
(SSTL)
(SSTL)
(SSTL)
Supply
Supply
Supply
Type
Input
Input
Negative
Negative
Positive
Positive
Polarity
Active
Active
Active
Active
Active
Active
Edge
Edge
Edge
High
High
High
High
and
Low
Low
-
-
-
-
-
The positive line of the differential pair of system clock inputs which drives the input to the
on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on the rising edge
of their associated clocks.
The negative line of the differential pair of system clock inputs which drives the input to the
on-DIMM PLL.
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode.
Enables the associated SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored but
previous operations continue.
When sampled at the positive rising edge of the clock,
executed by the SDRAM.
Reference voltage for SSTL-18 inputs
On-Die Termination control signals
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A12/A13 define the row address (RA0-RA12/RA13)
when sampled at the rising clock edge. A13 applies on 2GB SODIMM only.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when
sampled at the rising clock edge. In addition to the column address, AP is used to invoke
Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,
autoprecharge is selected and BA0/BA1/BA2 define the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1/BA2 to control
which bank(s) to precharge. If AP is high all 8 banks will be precharged regardless of the state of
BA0/BA1/BA2. If AP is low, then BA0/BA1/BA2 are used to define which bank to pre-charge.
Data and Check Bit Input/Output pins.
Power and ground for the DDR2 SDRAM input buffers and core logic
Data strobe for input and output data
The data write masks, associated with one data byte. In Write mode, DM operates as a byte
mask by allowing input data to be written if it is low but blocks the write operation if it is high. In
Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not
used on x64 modules.
Address inputs. Connected to either V
Presence Detect EEPROM address.
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be
connected from the SDA bus line to V
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from the SCL bus time to V
Serial EEPROM positive power supply.
5
DD
to act as a pull-up.
DD
DD
to act as a pull-up.
NANYA reserves the right to change products and specifications without notice.
or V
Function
SS
on the system board to configure the Serial
,
© NANYA TECHNOLOGY CORPORATION
,
define the operation to be