nt1gt64uh8d0fs-ad Nanya Techology, nt1gt64uh8d0fs-ad Datasheet - Page 19
nt1gt64uh8d0fs-ad
Manufacturer Part Number
nt1gt64uh8d0fs-ad
Description
Pc2-4200 / Pc2-5300 / Pc2-6400 Unbuffered Ddr2 So-dimm
Manufacturer
Nanya Techology
Datasheet
1.NT1GT64UH8D0FS-AD.pdf
(25 pages)
Note: Module IDD was calculated from component IDD. It may differ from the actual measurement.
NT512T64UH4D0FN / NT1GT64UH8D0FN / NT2GT64U8HD0BN
NT512T64UH4D0FS / NT1GT64UH8D0FS / NT2GT64U8HD0BS
512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64
PC2-4200 / PC2-5300 / PC2-6400
Unbuffered DDR2 SO-DIMM
Operating, Standby, and Refresh Currents
T
Symbol
IDD3PS
REV 1.2
03/2008
IDD3PF
IDD4W
IDD2Q
IDD2N
IDD3N
IDD4R
IDD2P
IDD5B
CASE
IDD0
IDD1
IDD6
IDD7
= 0 ° C ~ 85 °C; V
Operating Current: one bank; active/precharge; t
DQ, DM, and DQS inputs changing twice per clock cycle; address and
control inputs changing once per clock cycle
Operating Current: one bank; active/read/precharge; Burst = 4; t
(MIN)
once per clock cycle
Precharge Power-Down Standby Current: all banks idle; power-down
mode; CKE ≤ V
Precharge quiet standby current
Idle Standby Current: CS ≥ V
(MIN)
Active Power-Down Standby Current: one bank active; power-down
mode; CKE ≤ V
Active Power-Down Standby Current: one bank active; power-down
mode; CKE ≤ V
Active Standby Current: one bank; active/precharge; CS ≥ V
V
twice per clock cycle; address and control inputs changing once per clock
cycle
Operating Current: one bank; Burst = 4; reads; continuous burst; address
and control inputs changing once per clock cycle; DQ and DQS outputs
changing twice per clock cycle; CL = 4; t
Operating Current: one bank; Burst = 4; writes; continuous burst; address
and control inputs changing once per clock cycle; DQ and DQS inputs
changing twice per clock cycle; CL= 4; t
Burst Refresh Current: t
Self-Refresh Current: CKE ≤ 0.2V
Operating Current: four bank; four bank interleaving with BL = 4, address
and control inputs randomly changing; 50% of data changing at every
transfer; t
IH (MIN)
; CL= 4; t
; address and control inputs changing once per clock cycle
; t
RC
RC
= t
= t
CK
DDQ
RAS (MAX)
RC (min)
= t
IL (MAX)
IL (MAX)
IL (MAX)
= V
CK (MIN)
; I
DD
; t
; t
; t
; t
OUT
CK
CK
CK
CK
= 1.8V
; I
RC
Parameter/Condition
OUT
= t
= t
= t
= t
= 0mA.
= t
CK (MIN)
CK (MIN)
CK (MIN)
CK (MIN)
= 0mA; address and control inputs changing
IH (MIN)
RFC (MIN)
0.1V [2GB, 2 Ranks, 128Mx8 DDR2 SDRAMs]
; MRS(12)=0
; MRS(12)=1
; DQ, DM, and DQS inputs changing
; all banks idle; CKE ≥ V
CK
CK
= t
= t
CK (MIN)
CK (MIN)
RC
= t
; I
OUT
RC (MIN)
19
= 0mA
IH (MIN)
; t
IH (MIN)
CK
= t
; t
RC
; CKE ≥
CK
CK (MIN)
= t
= t
RC
CK
;
NANYA reserves the right to change products and specifications without notice.
PC2-4200
(-37B)
1204
1138
1396
1280
2208
2195
141
705
983
490
231
897
158
PC2-5300
(-3C)
1379
1293
1572
1417
2431
2593
1115
141
771
524
231
989
158
© NANYA TECHNOLOGY CORPORATION
PC2-6400
(-AD)
1556
1447
1252
1086
1740
1556
2523
2991
141
840
553
234
158
PC2-6400
(-AC)
1556
1447
1252
1086
1740
1556
2523
2991
141
840
553
234
158
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA