nt1gt64u8hb0by Nanya Techology, nt1gt64u8hb0by Datasheet - Page 18

• Manufacturer Part Number: nt1gt64u8hb0by
• Description: 256mb 32m X 64 / 512mb 64m X 64 / 1gb 128m X 64 Unbuffered Ddr2 Sdram Dimm
  
  
  
• Manufacturer: Nanya Techology

Note:
Symbol
I
I
I
I
I
I
I
I
NT256T64UH4B0FY / NT512T64U88B0BY / NT1GT64U8HB0BY
256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64
Unbuffered DDR2 SDRAM DIMM
Operating, Standby, and Refresh Currents
T
REV 1.2
03/2007
I
I
DD3PF
DD3PS
I
I
I
DD4W
DD2P
DD2N
DD2Q
DD3N
DD4R
Module IDD was calculated from component IDD. It may differ from the actual measurement.
CASE
DD0
DD1
DD5
DD6
DD7
= 0 ° C ~ 85 °C; V
Operating Current: one bank; active/precharge; t
(MIN);
and control inputs changing once per clock cycle
Operating Current: one bank; active/read/precharge; Burst = 2; t
(MIN);
changing once per clock cycle
Precharge Power-Down Standby Current: all banks idle; power-down
mode; CKE ≤ V
Idle Standby Current: CS ≥ V
= t
Precharge Quiet Standby Current: All banks idle;
HIGH; t
bus inputs are floating.
Active Power-Down Current: All banks open; t
LOW; Other control and address inputs are STABLE, Data bus inputs
are floating. MRS A12 bit is set to low (Fast Power-down Exit).
Active Power-Down Current: All banks open; t
LOW; Other control and address inputs are STABLE, Data bus inputs
are floating. MRS A12 bit is set to high (Slow Power-down Exit).
Active Standby Current: one bank; active/precharge; CS ≥ V
CKE ≥ V
inputs changing twice per clock cycle; address and control inputs
changing once per clock cycle
Operating Current: one bank; Burst = 2; writes; continuous burst;
address and control inputs changing once per clock cycle; DQ and DQS
inputs changing twice per clock cycle; CL=2.5; t
Operating Current: one bank; Burst = 2; reads; continuous burst;
address and control inputs changing once per clock cycle; DQ and DQS
outputs changing twice per clock cycle; CL = 2.5; t
0mA
Auto-Refresh Current: t
Self-Refresh Current: CKE ≤ 0.2V
Operating Current: four bank; four bank interleaving with BL = 4,
address and control inputs randomly changing; 50% of data changing at
every transfer; t
CK (MIN);
DQ, DM, and DQS inputs changing twice per clock cycle; address
CL=2.5; t
CK
IH (MIN);
= t
address and control inputs changing once per clock cycle
DDQ
CK (MIN)
CK
IL (MAX);
RC
= V
t
RC
= t
; Other control and address inputs are stable, Data
= t
DD
= t
CK (MIN);
RC
= 1.8V ± 0.1V (1GB, 2 Ranks, 64Mx8 DDR2 SDRAMs)
RAS (MAX)
RC
t
CK
(min); I
Parameter/Condition
= t
= t
IH (MIN);
RFC (MIN)
I
OUT
CK (MIN)
OUT
; t
= 0mA; address and control inputs
CK
= 0mA.
all banks idle; CKE ≥ V
= t
CK (MIN)
CK
CK
CK
; DQ, DM, and DQS
RC
= t
= t
CK
= t
= t
CK (MIN)
CK (MIN)
is HIGH; CKE is
CK (MIN)
= t
RC (MIN);
CK (MIN);
18
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
, CKE is
, CKE is
IH (MIN)
IH (MIN);
t
CK
RC
I
OUT
= t
= t
; t
CK
CK
=
RC
PC2-4200
(-37B)
1200
1240
1520
1600
880
960
112
640
560
448
144
664
112
PC2-5300
(-3C)
1000
1120
1520
1520
1680
1760
112
800
640
528
144
800
112
PC2-6400
(-25D)
1080
1208
1608
1568
1808
1768
112
816
720
624
144
888
112
© NANYA TECHNOLOGY CORP.
PC2-6400
(-25C)
1080
1208
1608
1568
1808
1768
112
816
720
624
144
888
112
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA