nt1gt72u8pb0by Nanya Techology, nt1gt72u8pb0by Datasheet - Page 16

• Manufacturer Part Number: nt1gt72u8pb0by
• Description: 240pin Unbuffered Ddr2 Sdram Module With Ecc Based On 64mx8 Ddr2 Sdram B Die
• Manufacturer: Nanya Techology

NT512T72U89B0BY / NT1GT72U8PB0BY
512MB: 64M x 72 / 1GB: 128M x 72
Unbuffered DDR2 SDRAM DIMM with ECC
Operating, Standby, and Refresh Currents
T
Note: Module IDD was calculated from component IDD. It may differ from the actual measurement.
REV 1.3
03/2007
Symbol
I
I
I
CASE
I
I
I
I
I
I
I
I
I
I
DD3PF
DD3PS
DD4W
DD2Q
DD2P
DD2N
DD3N
DD4R
DD5B
DD0
DD1
DD6
DD7
= 0 ° C ~ 85 °C; V
Operating Current: one bank; active/precharge; t
(MIN);
and control inputs changing once per clock cycle
Operating Current: one bank; active/read/precharge; Burst = 2; t
(MIN);
changing once per clock cycle
Precharge Power-Down Standby Current: all banks idle; power-down
mode; CKE ≤ V
Idle Standby Current: CS ≥ V
t
Precharge standby current; All banks idle; t
CS is high; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING.
Active Power-Down Standby Current: one bank active; power-down
mode; CKE ≤ V
Active Power-Down Standby Current: one bank active; power-down
mode; CKE ≤ V
Active Standby Current: one bank; active/precharge; CS ≥ V
CKE ≥ V
changing twice per clock cycle; address and control inputs changing
once per clock cycle
Operating Current: one bank; Burst = 2; writes; continuous burst;
address and control inputs changing once per clock cycle; DQ and DQS
inputs changing twice per clock cycle; CL=2.5; t
Operating Current: one bank; Burst = 2; reads; continuous burst;
address and control inputs changing once per clock cycle; DQ and DQS
outputs changing twice per clock cycle; CL = 2.5; t
0mA
Burst Refresh Current: t
Self-Refresh Current: CKE ≤ 0.2V
Operating Current: four bank; four bank interleaving with BL = 4,
address and control inputs randomly changing; 50% of data changing at
every transfer; t
CK
(MIN);
DQ, DM, and DQS inputs changing twice per clock cycle; address
CL=2.5; t
IH
address and control inputs changing once per clock cycle
(MIN);
DDQ
CK
IL (MAX);
IL
IL
RC
t
= V
RC
(MAX);
(MAX);
= t
= t
= t
CK
DD
RC
RAS
(MIN);
= 1.8V ± 0.1V (1GB, 2 Ranks, 64Mx8 DDR2 SDRAMs)
(min); I
t
t
t
RFC
CK
CK
CK
Parameter/Condition
(MAX)
= t
= t
= t
= t
I
OUT
IH
CK
CK
CK
RFC (MIN)
OUT
; t
(MIN);
(MIN); Fast PDN Exit MRS(12) = 0mA
(MIN); Slow PDN Exit MRS(12) = 1mA
(MIN)
= 0mA; address and control inputs
CK
= 0mA.
= t
all banks idle; CKE ≥ V
CK
(MIN)
CK
; DQ, DM, and DQS inputs
= t
CK
RC
CK
= t
CK
= t
(IDD); CKE is high;
CK
= t
RC
(MIN)
CK
(MIN);
16
(MIN);
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
IH
IH
(MIN)
t
(MIN);
CK
I
RC
OUT
= t
; t
= t
CK
=
CK
RC
=
PC2-4200
(-37B)
1080
1350
1350
1710
1800
990
126
720
630
504
162
747
126
PC2-5300
(-3C)
1125
1260
1710
1620
1890
1980
126
900
720
594
162
900
126
PC2-6400
(-25C)
1224
1359
1809
1764
2034
1989
126
918
810
702
162
999
126
© NANYA TECHNOLOGY CORP.
PC2-6400
(-25D)
1224
1359
1809
1764
2034
1989
126
918
810
702
162
999
126
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA