nt1gt72u89d0bv Nanya Techology, nt1gt72u89d0bv Datasheet - Page 11

• Manufacturer Part Number: nt1gt72u89d0bv
• Description: Based On Ddr2-667/800 128mx8 1gb/2gb And 256mx4 2gb/4gb Sdram D-die
• Manufacturer: Nanya Techology

NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV
NT2GT72U8PD0BV
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72
PC2-5300 / PC3-6400
Registered DDR2 SDRAM DIMM
REV 1.1
01/2009
Serial Presence Detect
Byte
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
0
1
2
3
4
5
6
7
8
9
Number of Serial PD Bytes Written during Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Ranks
Data Width of Assembly
Reserved
Voltage Interface Level of this Assembly
DDR2 SDRAM Device Cycle Time at CL=X
DDR2 SDRAM Device Access Time from Clock at CL=X
DIMM Configuration Type
Refresh Rate/Type
Primary DDR2 SDRAM Width
Error Checking DDR2 SDRAM Device Width
Reserved
DDR2 SDRAM Device Attributes: Burst Length Supported
DDR2 SDRAM Device Attributes: Number of Device Banks
DDR2 SDRAM Device Attributes: CAS Latencies Supported
DIMM Mechanical Characteristics
DDR2 SDRAM DIMM Type Information
DDR2 SDRAM Module Attributes:
DDR2 SDRAM Device Attributes: General
Minimum Clock Cycle at CL=X-1
Maximum Data Access Time from Clock at CL=X-1
Minimum Clock Cycle Time at CL=X-2
Maximum Data Access Time from Clock at CL=X-2
Minimum Row Precharge Time (t
Minimum Row Active to Row Active delay (t
Minimum RAS to CAS delay (t
Minimum RAS Pulse Width (t
Module Bank Density
Address and Command Setup Time Before Clock (t
Address and Command Hold Time After Clock (t
Data Input Setup Time Before Clock (t
Data Input Hold Time After Clock (t
Write Recovery Time (t
Internal Write to Read Command delay (t
Internal Read to Precharge delay (t
Reserved
Extension of Byte 41 t
Minimum Core Cycle Time (t
Min. Auto Refresh Command Cycle Time (t
Maximum Clock Cycle Time (t
Max. DQS-DQ Skew Factor (t
Read Data Hold Skew Factor (t
PLL Relock Time
Tcasemax, DT4R4W Delta
Thermal Resistance of DRAM Package from Top (Case) to
Ambient (Psi T-A DRAM)
DRAM Case Temperature Rise from Ambient due to Activate-
Precharge/Mode Bits (DT0/Mode Bits)
DRAM Case Temperature Rise from Ambient due to
Precharge/Quiet Standby (DT2N/DT2Q)
DRAM Case Temperature Rise from Ambient due to precharge
Power-Down (DT2P)
DRAM Case Temperature Rise from Ambient due to Active
Standby (DT3N)
DRAM Case Temperature Rise from Ambient due to Active Power-
Down with Fast PDN Exit (DT3P fast)
RC
WR
(Part 1 of 2) [NT2GT72U4PD0BV, 2GB – 1 Rank, 256Mx4 DDR2 SDRAMs]
and Byte 42 t
)
Description
RC
RAS
DQS
CK
RCD
)
QHS
)
)
RP
)
)
)
)
DH
RTP
)
)
RFC
DS
)
WTR
RFC
RRD
)
)
)
IH
)
IS
)
FET Switch External Enable : No,
Module Height = 30.0mm, 1 rank Module Height = 30.0mm, 1 rank
Number of Active Registers : 2,
Analysis probe installed : No,
The number below a decimal
point of tRC and tRFC are 0,
Address/Command Parity,
tRFC is less than 256ns.
Supports 50 ohm ODT,
Supports Weak Driver,
RDIMM (133.35mm)
Number of PLLs : 1,
11
Non Data Parity,
Supports PASR,
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
DDR2 SDRAM
x B 4.10 (mm)
SSTL 1.8V
Data ECC,
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
127.5ns
0.45ns
3.75ns
0.27ns
0.17ns
0.24ns
0.34ns
7.8 As
0.5ns
0.6ns
7.5ns
0.2ns
0.1ns
7.5ns
7.5ns
3,4,5
15ns
15ns
45ns
15ns
60ns
15As
2GB
128
256
X72
3ns
5ns
8ns
-3C
X4
X4
4,8
14
11
8
SPD Entry Value
FET Switch External Enable : No,
Number of Active Registers : 2,
Analysis probe installed : No,
The number below a decimal
point of tRC and tRFC are 0,
Address/Command Parity,
tRFC is less than 256ns.
Supports 50 ohm ODT,
Supports Weak Driver,
RDIMM (133.35mm)
Number of PLLs : 1,
Non Data Parity,
Supports PASR,
DDR2 SDRAM
x B 4.10 (mm)
SSTL 1.8V
Data ECC,
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
127.5ns
0.45ns
3.75ns
0.17ns
0.25ns
0.05ns
0.12ns
7.8 As
2.5ns
0.4ns
0.5ns
7.5ns
7.5ns
7.5ns
0.2ns
0.3ns
4,5,6
15As
15ns
15ns
45ns
2GB
15ns
60ns
-AD
X72
128
256
3ns
8ns
4,8
14
11
X4
X4
8
© NANYA TECHNOLOGY CORP.
Serial PD Data Entry (Hex.)
-3C
0E
0B
0C
3D
3C
1E
3C
2D
3C
1E
1E
3C
80
08
08
60
48
00
05
30
45
06
82
04
04
00
08
38
01
01
05
07
50
50
60
02
20
27
10
17
00
06
7F
80
18
22
0F
00
00
00
00
00
00
00
-AD
0E
0B
0C
3D
3C
1E
3C
2D
3C
1E
1E
3C
7F
1E
0F
80
08
08
60
48
00
05
25
40
06
82
04
04
00
08
70
01
01
05
07
30
45
50
02
17
25
05
12
00
06
80
14
00
00
00
00
00
00
00