s29gl01gs Meet Spansion Inc., s29gl01gs Datasheet - Page 37

• Manufacturer Part Number: s29gl01gs
• Manufacturer: Meet Spansion Inc.

March 21, 2011 S29GL_128S_01GS_00_02
5.4.2
5.4.2.1
Data Polling Status
Notes:
1. Bits 15 thru 8, and 0 are reserved for future use and may display as 0 or 1. These bits should be ignored (masked) when checking status.
2. Bit 7 is 1 when there is no Embedded Algorithm in progress in the device.
3. Bits 6 thru 1 are valid only if Bit 7 is 1.
4. All bits are put in their reset status by cold reset or warm reset.
5. Bits 5, 4, 3, and 1 are cleared to 0 by the Clear Status Register command or Reset command.
6. Upon issuing the Erase Suspend Command, the user must continue to read status until DRB becomes 1.
7. ESSB is cleared to 0 by the Erase Resume Command.
8. ESB reflects success or failure of the most recent erase operation.
9. PSB reflects success or failure of the most recent program operation.
10. During erase suspend, programming to the suspended sector, will cause program failure and set the Program status bit to 1.
11. Upon issuing the Program Suspend Command, the user must continue to read status until DRB becomes 1.
12. PSSB is cleared to 0 by the Program Resume Command.
13. SLSB indicates that a program or erase operation failed because the sector was locked.
14. SLSB reflects the status of the most recent program or erase operation.
During an active Embedded Algorithm the EAC switches to the Data Polling ASO to display EA status to any
read access. A single word of status information is aliased in all locations of the device address space. In the
status word there are several bits to determine the status of an EA. These are referred to as DQ bits as they
appear on the data bus during a read access while an EA is in progress. DQ bits 15 to 8, DQ4, and DQ0 are
reserved and provide undefined data. Status monitoring software must mask the reserved bits and treat them
as don't care.
bits.
Note that in future technology nodes the Data Polling Status feature will not be supported. The user is
strongly advised to use the Status Register to determine device status.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or
has completed. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase
command sequence. Note that the Data# Polling is valid only for the last word being programmed in the write-
buffer-page during Write Buffer Programming. Reading Data# Polling status on any word other than the last
word to be programmed in the write-buffer-page will return false status information.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the data bit
programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device outputs the data bit programmed to bit 7 of the last
word programmed. In case of a Program Suspend, the device allows only reading array data. If a program
address falls within a protected sector, Data# Polling on DQ7 is active for approximately 20 µs, then the
device returns to reading array data.
Busy Status
Description
Bit Name
Status
Ready
Status
Reset
Bit #
Bit
D a t a
Reserved
Invalid
Table 5.3 on page 41
15:8
X
X
S h e e t
Ready Bit
Device
DRB
7
1
0
1
0=No Erase
Suspension
Suspension
1=Erase in
GL-S MirrorBit
( P r e l i m i n a r y )
Status Bit
Suspend
Invalid
Erase
ESSB
and the following subsections describe the functions of the remaining
in
6
0
Table 5.2 Status Register
1=Erase fail
successful
Status Bit
0=Erase
Invalid
Erase
ESB
®
5
0
Family
0=Program
1=Program
successful
Status Bit
Program
Invalid
PSB
fail
4
0
Write Buffer
not aborted
0=Program
1=Program
command
Status Bit
WBASB
aborted
Write to
Invalid
during
Buffer
Abort
3
0
suspension
1=Program
suspension
Program in
Status Bit
Suspend
Program
Invalid
PSSB
0=No
in
2
0
Sector Lock
locked error
not locked
Status Bit
0=Sector
operation
1=Sector
Invalid
during
SLSB
1
0
Reserved
Invalid
X
0
0
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