s29gl01gs Meet Spansion Inc., s29gl01gs Datasheet - Page 64

• Manufacturer Part Number: s29gl01gs
• Manufacturer: Meet Spansion Inc.

8.3
8.4
64
8.3.1
8.3.2
8.4.1
8.4.2
Power Conservation Modes
Read
Interface Standby
Automatic Sleep
Read With Output Disable
Random (Asynchronous) Read
Standby is the default, low power, state for the interface while the device is not selected by the host for data
transfer (CE# = High). All inputs are ignored in this state and all outputs except RY/BY# are high impedance.
RY/BY# is a direct output of the EAC, not controlled by the Host Interface.
The automatic sleep mode reduces device interface energy consumption to the sleep level (I
the completion of a random read access time. The device automatically enables this mode when addresses
remain stable for t
system. Output of the data depends on the level of the OE# signal but, the automatic sleep mode current is
independent of the OE# signal level. Standard address access timings (t
addresses are changed. I
specification.
Automatic sleep helps reduce current consumption especially when the host system clock is slowed for power
reduction. During slow system clock periods, read and write cycles may extend many times their length
versus when the system is operating at high speed. Even though CE# may be Low throughout these
extended data transfer cycles, the memory device host interface will go to the Automatic Sleep current at t
+ 30 ns. The device will remain at the Automatic Sleep current for t
standby current level. This keeps the memory at the Automatic Sleep or standby power level for most of the
long duration data transfer cycles, rather than consuming full read power all the time that the memory device
is selected by the host system.
However, the EAC operates independent of the automatic sleep mode of the host interface and will continue
to draw current during an active Embedded Algorithm. Only when both the host interface and EAC are in their
standby states is the standby level current achieved.
When the CE# signal is asserted Low, the host system memory controller begins a read or write data transfer.
Often there is a period at the beginning of a data transfer when CE# is Low, Address is valid, OE# is High,
and WE# is High. During this state a read access is assumed and the Random Read process is started while
the data outputs remain at high impedance. If the OE# signal goes Low, the interface transitions to the
Random Read state, with data outputs actively driven. If the WE# signal is asserted Low, the interface
transitions to the Write state. Note, OE# and WE# should never be Low at the same time to ensure no data
bus contention between the host system and memory.
When the host system interface selects the memory device by driving CE# Low, the device interface leaves
the Standby state. If WE# is High when CE# goes Low, a random read access is started. The data output
depends on the address map mode and the address provided at the time the read access is started.
The data appears on DQ15-DQ0 when CE# is Low, OE# is Low, WE# remains High, address remains stable,
and the asynchronous access times are satisfied. Address access time (t
stable addresses to valid output data. The chip enable access time (t
data at the outputs. In order for the read data to be driven on to the data outputs the OE# signal must be Low
at least the output enable time (t
At the completion of the random access time from CE# active (t
(t
map mode. If CE# remains Low and any of the
random read access begins. If CE# remains Low and OE# goes High the interface transitions to the Read
with Output Disable state. If CE# remains Low, OE# goes High, and WE# goes Low, the interface transitions
OE
), whichever occurs latest, the data outputs will provide valid read data from the currently active address
ACC
+ 30 ns. While in sleep mode, output data is latched and always available to the
CC6
in
D a t a
DC Characteristics on page 69
OE
GL-S MirrorBit
) before valid data is available.
S h e e t
A
®
MAX
Family
to A4 address signals change to a new value, a new
( P r e l i m i n a r y )
represents the automatic sleep mode current
CE
), address stable (t
ASSB
S29GL_128S_01GS_00_02 March 21, 2011
CE
) is the delay from stable CE# to valid
. Then the device will transition to the
ACC
ACC
or t
) is equal to the delay from
PACC
) provide new data when
ACC
), or OE# active
CC6
) following
ACC