s29al008d Meet Spansion Inc., s29al008d Datasheet - Page 21

• Manufacturer Part Number: s29al008d
• Description: 8 Megabit 1 M X 8-bit/512 K X 16-bit Cmos 3.0 Volt-only Boot Sector Flash Memory
• Manufacturer: Meet Spansion Inc.

7.12
8. Command Definitions
8.1
November 27, 2007 S29AL008D_00_A10
7.12.1
7.12.2
7.12.3
7.12.4
Hardware Data Protection
Reading Array Data
Low V
Write Pulse Glitch Protection
Logical Inhibit
Power-Up Write Inhibit
The command sequence requirement of unlock cycles for programming or erasing provides data protection
against inadvertent writes (refer to
hardware data protection measures prevent accidental erasure or programming, which might otherwise be
caused by spurious system level signals during V
noise.
When V
power-up and power-down. The command register and all internal program/erase circuits are disabled, and
the device resets. Subsequent writes are ignored until V
proper signals to the control pins to prevent unintentional writes when V
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Write cycles are inhibited by holding any one of OE# = V
CE# and WE# must be a logical zero while OE# is a logical one.
If WE# = CE# = V
edge of WE#. The internal state machine is automatically reset to reading array data on power-up.
Writing specific address and data commands or sequences into the command register initiates device
operations.
and data values or writing them in the improper sequence resets the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the
Characteristics on page
The device is automatically set to reading array data after device power-up. No commands are required to
retrieve data. The device is also ready to read array data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The
system can read array data using the standard read timings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data. After completing a programming operation in the Erase
Suspend mode, the system may once again read array data with the same exception. See
Erase Resume Commands on page 25
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or
while in the autoselect mode. See
See also
Operations on page 36
CC
CC
Requirements for Reading Array Data on page 14
Write Inhibit
is less than V
Table 8.1 on page 26
IL
and OE# = V
provides the read parameters, and
36.
LKO
D a t a
, the device does not accept any write cycles. This protects data during V
IH
defines the valid register command sequences. Writing incorrect address
Reset Command on page
Table 8.1 on page 26
S h e e t
during power up, the device does not accept commands on the rising
S29AL008D
for more information on this mode.
CC
power-up and power-down transitions, or from system
CC
IL
for command definitions). In addition, the following
, CE# = V
is greater than V
Figure 15.1 on page 36
for more information.
22.
IH
or WE# = V
CC
LKO
is greater than V
. The system must provide the
Table 15.1, Read
IH
shows the timing diagram.
. To initiate a write cycle,
Erase Suspend/
LKO
.
CC
AC
21