s6b0724 Densitron Corporation, s6b0724 Datasheet - Page 16

• Manufacturer Part Number: s6b0724
• Description: 132 Seg / 65 Com Driver & Controller For Stn Lcd
• Manufacturer: Densitron Corporation

132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
MICROPROCESSOR INTERFACE
12
RW_WRB
RESETB
Name
CS1B
CS2
C68
PS
RS
I/O
I
I
I
I
I
I
Reset input pin
When RESETB is "L", initialization is executed.
Parallel / Serial data input select input
*NOTE: In serial mode, it is impossible to read data from the on-chip RAM. And DB0 to DB5
are high impedance and E_RDB and RW_WRB must be fixed to either "H" or "L".
Microprocessor Interface Select input pin in parallel mode
Chip select input pins
Data / instruction I/O is enabled only when CS1B is "L" and CS2 is "H". When chip
select is non-active, DB0 to DB7 may be high impedance.
Register select input pin
Read / Write execution control pin
C68
PS
C68 = "H": 6800-series MPU interface
C68 = "L": 8080-series MPU interface
RS = "H": DB0 to DB7 are display data
RS = "L": DB0 to DB7 are control data
H
H
L
L
Table 6. Microprocessor Interface Pins Description
6800-series
8080-series
Interface
MPU Type
Parallel
mode
Serial
CS1B,
CS1B,
select
Chip
CS2
CS2
RW_WRB
/WRB
RW
instruction
Data /
RS
RS
PRELIMINARY SPEC. VER. 1.1
Read / Write control input pin
Write enable clock input pin
The data on DB0 to DB7 are latched at the rising
edge of the /WRB signal.
Description
RW = "H": read
RW = "L": write
DB0 to DB7
SID (DB7)
Data
Description
Read / Write
RW_WRB
Write only
E_RDB
SCLK (DB6)
Serial clock
S6B0724
-