fs6370 AMI Semiconductor, Inc., fs6370 Datasheet - Page 3

• Manufacturer Part Number: fs6370
• Description: Fs6370-01g Eeprom Programmable 3-pll Clock Generator Ic
• Manufacturer: AMI Semiconductor, Inc.

www.amis.com.
F F S S 6 6 3 3 7 7 0 0 - - 0 0 1 1 / / F F S S 6 6 3 3 7 7 0 0 - - 0 0 1 1 g g E E E E P P R R O O M M P P r r o o g g r r a a m m m m a a b b l l e e 3 3 - - P P L L L L C C l l o o c c k k G G e e n n e e r r a a t t o o r r I I C C
A A M M I I S S e e m m i i c c o o n n d d u u c c t t o o r r - - R R e e v v . . 2 2 . . 0 0 , , M M a a r r . . 0 0 5 5
3.0 Functional Block Description
3 3 . . 1 1 P P h h a a s s e e L L o o c c k k e e d d L L o o o o p p s s ( ( P P L L L L s s ) )
Each of the three on-chip PLLs is a standard phase- and frequency-locked loop architecture that multiplies a reference frequency to a desired frequency by
a ratio of integers. This frequency multiplication is exact.
As shown in Figure 3, each PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an internal loop filter, a voltage-controlled
oscillator (VCO), and a feedback divider.
During operation, the reference frequency (f
often referred to as the modulus, and is denoted as N
The PFD controls the frequency of the VCO (f
frequency clock source for the PLL. The output of the VCO is fed back to the PFD through the feedback divider (the modulus is denoted by N
the loop.
The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at the inputs of the
PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is:
3.1.1 Reference Divider
The reference divider is designed for low phase jitter. The divider accepts the output of the reference oscillator and provides a divided-down frequency to
the PFD. The reference divider is an 8-bit divider, and can be programmed for any modulus from 1 to 255 by programming the equivalent binary value.
A divide-by-256 can also be achieved by programming the eight bits to 00h.
3.1.2 Feedback Divider
The feedback divider is based on a dual-modulus pre-scaler technique. The technique allows the same granularity as a fully programmable feedback divider,
while still allowing the programmable portion to operate at low speed. A high-speed pre-divider (also called a pre-scaler) is placed between the VCO and
the programmable feedback divider because of the high speeds at which the VCO can operate. The dual-modulus technique insures reliable operation at
any speed that the VCO can achieve and reduces the overall power consumption of the divider.
f
REF
VCO
REF
), generated by the on-board crystal oscillator, is first reduced by the reference divider. The divider value is
) through the charge pump and loop filter. The VCO provides a high-speed, low noise, continuously variable
Reference
REFDIV[7:0]
Divider
(N
R
)
R
for the reference divider. The divided reference is fed into the PFD.
f
PD
Frequency
Detector
f
Phase-
Figure 3: PLL Block Diagram
VCO
=
f
3
REF
Divider
Feedback
FBKDIV[10:0]
UP
DOWN
Charge
æ
ç ç
è
Pump
N
N
CP
(N
F
R
F
)
ö
÷ ÷
ø
Controlled
Oscillator
Voltage
Loop
Filter
LFTC
f
VCO
Data Sheet
F
) to close