mbm29dl324te90tr Meet Spansion Inc., mbm29dl324te90tr Datasheet - Page 41

• Manufacturer Part Number: mbm29dl324te90tr
• Description: 32 M 4 M ? 8/2 M ? 16 Bit Dual Operation Flash Memory
• Manufacturer: Meet Spansion Inc.

MBM29DL32XTE/BE
80 / 90
• RESET
Hardware Reset
The MBM29DL32XTE/BE devices may be reset by driving the RESET pin to V
. The RESET pin has a pulse
IL
requirement and has to be kept low (V
) for at least “t
” in order to properly reset the internal state machine.
IL
RP
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode “t
” after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
READY
devices require an additional “t
” before it will allow read access. When the RESET pin is low, the devices will
RH
be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please
note that the RY/BY output signal should be ignored during the RESET pulse. See “RESET, RY/BY Timing
Diagram” in “■ TIMING DIAGRAM” for the timing diagram. Refer to Temporary Sector Group Unprotection for
additional functionality.
• Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29DL32XTE/BE devices. When
this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ
0
to DQ
. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ
/A-
pin
15
15
1
becomes the lowest address bit and DQ
to DQ
bits are tri-stated. However, the command bus cycle is always
8
14
an 8-bit operation and hence commands are written at DQ
to DQ
and the DQ
to DQ
bits are ignored. Refer
0
7
8
15
to “Timing Diagram for Word Mode Configuration”, “Timing Diagram for Byte Mode Configuration” and “BYTE
Timing Diagram for Write Operations” in “■ TIMING DIAGRAM” for the timing diagram.
• Boot Block Sector Protection
The Write Protection function provides a hardware method of protecting certain boot sectors without using V
.
ID
This function is one of two provided by the WP/ACC pin.
If the system asserts V
on the WP/ACC pin, the device disables program and erase functions in the two
IL
“outermost” 8 Kbyte boot sectors (MBM29DL32XTE : SA69 and SA70, MBM29DL32XBE : SA0 and SA1)
independently of whether those sectors were protected or unprotected using the method described in “Sector
Group Protection”. The two outermost 8 Kbyte boot sectors are the two sectors containing the lowest addresses
in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured
device.
If the system asserts V
on the WP/ACC pin, the device reverts to whether the two outermost 8 Kbyte boot
IH
sectors were last set to be protected or unprotected. That is, sector group protection or unprotection for these
two sectors depends on whether they were last protected or unprotected using the method described in “Sector
Group Protection”.
• Accelerated Program Operation
MBM29DL32XTE/BE offers accelerated program operation which enables the programming in high speed.
If the system asserts V
to the WP/ACC pin, the device automatically enters the acceleration mode and the
ACC
time required for program operation will reduce to about 60%. This function is primarily intended to allow high
speed program, so caution is needed as the sector group will temporarily be unprotected.
The system would use a fact program command sequence when programming during acceleration mode.
Set command to fast mode and reset command from fast mode are not necessary. When the device enters the
acceleration mode, the device automatically set to fast mode. Therefore, the present sequence could be used
for programming and detection of completion during acceleration mode.
Removing V
from the WP/ACC pin returns the device to normal operation. Do not remove V
from
ACC
ACC
WP/ACC pin while programming. See “Accelerated Program Timing Diagram” in “■ TIMING DIAGRAM”.
Erase operation during Accelerated Program Operation is strictly prohibited.
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Retired Product DS05-20881-8E_July 20, 2007